LM3S101 Luminary Micro, Inc., LM3S101 Datasheet - Page 12

• Manufacturer Part Number: LM3S101
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

List of Registers
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Universal Asynchronous Receiver/Transmitter (UART) ........................................................... 190
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Synchronous Serial Interface (SSI) ............................................................................................. 226
Register 1:
Register 2:
Register 3:
Register 4:
12
Watchdog Control (WDTCTL), offset 0x008............................................................................ 172
Watchdog Interrupt Clear (WDTICR), offset 0x00C ................................................................ 173
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 ....................................................... 174
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014.................................................. 175
Watchdog Lock (WDTLOCK), offset 0xC00 ............................................................................ 176
Watchdog Test (WDTTEST), offset 0x418 .............................................................................. 177
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0..................................... 178
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4..................................... 179
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8..................................... 180
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC .................................... 181
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ..................................... 182
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ..................................... 183
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ..................................... 184
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC .................................... 185
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0........................................ 186
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4........................................ 187
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8........................................ 188
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC ...................................... 189
UART Data (UARTDR), offset 0x000 ...................................................................................... 197
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 .............................. 199
UART Flag (UARTFR), offset 0x018 ....................................................................................... 201
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ................................................. 203
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ........................................... 204
UART Line Control (UARTLCRH), offset 0x02C ..................................................................... 205
UART Control (UARTCTL), offset 0x030................................................................................. 207
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ................................................ 208
UART Interrupt Mask (UARTIM), offset 0x038 ........................................................................ 209
UART Raw Interrupt Status (UARTRIS), offset 0x03C............................................................ 211
UART Masked Interrupt Status (UARTMIS), offset 0x040 ...................................................... 212
UART Interrupt Clear (UARTICR), offset 0x044...................................................................... 213
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0.......................................... 214
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4.......................................... 215
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8.......................................... 216
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ......................................... 217
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0.......................................... 218
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4.......................................... 219
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8.......................................... 220
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ......................................... 221
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0............................................. 222
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4............................................. 223
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8............................................. 224
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ............................................ 225
SSI Control 0 (SSICR0), offset 0x000 ..................................................................................... 238
SSI Control 1 (SSICR1), offset 0x004 ..................................................................................... 240
SSI Data (SSIDR), offset 0x008 .............................................................................................. 242
SSI Status (SSISR), offset 0x00C ........................................................................................... 243
Preliminary
October 5, 2006