LM3S101 Luminary Micro, Inc., LM3S101 Datasheet - Page 212

• Manufacturer Part Number: LM3S101
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Universal Asynchronous Receiver/Transmitter (UART)
212
Reset
Reset
Type
Type
Bit/Field
31:11
UART Masked Interrupt Status (UARTMIS)
Offset 0x040
3:0
10
9
8
7
6
5
4
RO
RO
31
15
0
0
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
RO
RO
30
14
0
0
reserved
reserved
OEMIS
RXMIS
BEMIS
PEMIS
FEMIS
RTMIS
TXMIS
Name
reserved
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
27
11
0
0
OEMIS
RO
RO
26
10
0
0
Reset
0
0
0
0
0
0
0
0
0
BEMIS
RO
RO
25
0
9
0
Preliminary
Reserved bits return an indeterminate value, and should never
Reserved bits return an indeterminate value, and should never
Description
be changed.
UART Overrun Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Break Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Parity Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Framing Error Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Receive Time-Out Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Transmit Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
UART Receive Masked Interrupt Status
Gives the masked interrupt state of this interrupt.
be changed.
PEMIS
RO
RO
24
0
8
0
reserved
FEMIS
RO
RO
23
0
7
0
RTMIS
RO
RO
22
0
6
0
TXMIS RXMIS
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
RO
RO
18
0
2
0
reserved
October 5, 2006
RO
RO
17
0
1
0
RO
RO
16
0
0
0