LM3S102-IRN20(T) Luminary Micro, Inc., LM3S102-IRN20(T) Datasheet - Page 211

• Manufacturer Part Number: LM3S102-IRN20(T)
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

October 6, 2006
Reset
Reset
Type
Type
Bit/Field
31:6
UART Interrupt FIFO Level Select (UARTIFLS)
Offset 0x034
5:3
2:0
RO
RO
31
15
0
0
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to
define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an
interrupt at the half-way mark.
RO
RO
30
14
0
0
RXIFLSEL
TXIFLSEL
reserved
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
Type
R/W
R/W
RO
RO
RO
27
11
0
0
reserved
RO
RO
26
10
0
0
Reset
0X2
0X2
0
RO
RO
25
0
9
0
Preliminary
Description
Reserved bits return an indeterminate value, and should never
be changed.
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
000: RX FIFO
001: RX FIFO
010: RX FIFO
011: RX FIFO
100: RX FIFO
101-111: Reserved
UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
000: TX FIFO
001: TX FIFO
010: TX FIFO
011: TX FIFO
100: TX FIFO
101-111: Reserved
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
3/4 full
3/4 full
1/8 full
1/4 full
1/2 full (default)
7/8 full
RO
RO
1/8 full
1/4 full
1/2 full (default)
7/8 full
22
0
6
0
R/W
RO
21
0
5
0
RXIFLSEL
R/W
RO
20
0
4
1
R/W
RO
19
0
3
0
LM3S102 Data Sheet
R/W
RO
18
0
2
0
TXIFLSEL
R/W
RO
17
0
1
1
R/W
RO
16
0
0
0
211