LM3S102-IRN20(T) Luminary Micro, Inc., LM3S102-IRN20(T) Datasheet - Page 32

• Manufacturer Part Number: LM3S102-IRN20(T)
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

ARM Cortex-M3 Processor Core
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.6.1
2.2.6.2
32
Embedded Trace Macrocell (ETM)
ETM was not implemented in the Stellaris devices. This means Chapters 15 and 16 of the ARM®
Cortex™-M3 Technical Reference Manual can be ignored.
Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer. The Stellaris devices have implemented TPIU as shown in Figure 2-2. This is
similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference Manual,
however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram
ROM Table
The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical
Reference Manual.
Memory Protection Unit (MPU)
The LM3S102 controller does not include the memory protection unit (MPU) of the ARM Cortex-
M3.
Nested Vectored Interrupt Controller (NVIC)
Interrupts
The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of
interrupts and interrupt priorities. The LM3S102 microcontroller supports 14 interrupts with eight
priority levels.
SysTick Calibration Value Registers
The SysTick Calibration Value register is not implemented.
Debug
Slave
Slave
ATB
APB
Port
Port
Interface
Interface
ATB
APB
Preliminary
Asynchronous FIFO
(serializer)
Trace Out
Serial Wire
Trace Port
(SWO)
October 6, 2006