LM3S102-IRN20(T) Luminary Micro, Inc., LM3S102-IRN20(T) Datasheet - Page 36
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LM3S102-IRN20(T)
Manufacturer Part Number
LM3S102-IRN20(T)
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S102-IRN20T.pdf
(335 pages)
- Current page: 36 of 335
- Download datasheet (2Mb)
Interrupts
36
Table 4-1. Exception Types (Continued)
a. 0 is the default priority for all the settable priorities.
Table 4-2. Interrupts
Exception Type
Usage Fault
-
SVCall
Debug Monitor
-
PendSV
SysTick
Interrupts
(Bit in Interrupt Registers)
Interrupt
9-17
3-4
18
19
20
21
0
1
2
5
6
7
8
Position
16 and
above
7
12
13
14
15
11
-
6
10
Description
GPIO Port A
GPIO Port B
GPIO Port C
Reserved
UART0
Reserved
SSI
I
Reserved
Watchdog timer
Timer0a
Timer0b
Timer1a
2
C
Priority
settable
settable
settable
settable
settable
settable
Preliminary
-
-
a
Description
Usage fault, such as undefined instruction executed
or illegal state transition attempt. This is
synchronous.
Reserved.
System service call with SVC instruction. This is
synchronous.
Debug monitor (when not halting). This is
synchronous, but only active when enabled. It does
not activate if lower priority than the current
activation.
Reserved.
Pendable request for system service. This is
asynchronous and only pended by software.
System tick timer has fired. This is asynchronous.
Asserted from outside the ARM Cortex
fed through the NVIC (prioritized). These are all
asynchronous. Table 4-2 lists the interrupts on the
LM3S102 controller.
-
M3 core and
October 6, 2006
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