LM3S2110-IQN20-A0 Luminary Micro, Inc., LM3S2110-IQN20-A0 Datasheet - Page 297
LM3S2110-IQN20-A0
Manufacturer Part Number
LM3S2110-IQN20-A0
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S2110-IQN20-A0.pdf
(485 pages)
- Current page: 297 of 485
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SSI Raw Interrupt Status (SSIRIS)
SSI0 base: 0x4000.8000
Offset 0x018
Type RO, reset 0x0000.0008
November 29, 2007
Reset
Reset
Type
Type
Bit/Field
31:4
3
2
1
0
RO
RO
31
15
0
0
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
RO
RO
30
14
0
0
reserved
RORRIS
RXRIS
RTRIS
TXRIS
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
RO
RO
RO
26
10
0
0
reserved
Reset
0x00
1
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Transmit FIFO Raw Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
SSI Receive FIFO Raw Interrupt Status
Indicates that the receive FIFO is half full or more, when set.
SSI Receive Time-Out Raw Interrupt Status
Indicates that the receive time-out has occurred, when set.
SSI Receive Overrun Raw Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
LM3S2110 Microcontroller
TXRIS
RO
RO
19
0
3
1
RXRIS
RO
RO
18
0
2
0
RTRIS
RO
RO
17
0
1
0
RORRIS
RO
RO
16
0
0
0
297
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