LM3S2110-IQN20-A0 Luminary Micro, Inc., LM3S2110-IQN20-A0 Datasheet - Page 8

• Manufacturer Part Number: LM3S2110-IQN20-A0
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Table of Contents
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 7-1.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 11-1.
Figure 11-2.
Figure 11-3.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 12-4.
Figure 12-5.
Figure 12-6.
Figure 12-7.
Figure 12-8.
Figure 12-9.
Figure 12-10. MICROWIRE Frame Format (Single Frame) .................................................................... 283
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 284
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 284
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 13-9.
Figure 13-10. Master Burst RECEIVE .................................................................................................. 320
Figure 13-11. Master Burst RECEIVE after Burst SEND ........................................................................ 321
Figure 13-12. Master Burst SEND after Burst RECEIVE ........................................................................ 322
8
Stellaris
CPU Block Diagram ......................................................................................................... 34
TPIU Block Diagram ........................................................................................................ 35
JTAG Module Block Diagram ............................................................................................ 44
Test Access Port State Machine ....................................................................................... 47
IDCODE Register Format ................................................................................................. 52
BYPASS Register Format ................................................................................................ 53
Boundary Scan Register Format ....................................................................................... 53
External Circuitry to Extend Reset .................................................................................... 55
Flash Block Diagram ...................................................................................................... 110
GPIO Port Block Diagram ............................................................................................... 135
GPIODATA Write Example ............................................................................................. 136
GPIODATA Read Example ............................................................................................. 136
GPTM Module Block Diagram ........................................................................................ 176
16-Bit Input Edge Count Mode Example .......................................................................... 180
16-Bit Input Edge Time Mode Example ........................................................................... 181
16-Bit PWM Mode Example ............................................................................................ 182
WDT Module Block Diagram .......................................................................................... 211
UART Module Block Diagram ......................................................................................... 235
UART Character Frame ................................................................................................. 236
IrDA Data Modulation ..................................................................................................... 238
SSI Module Block Diagram ............................................................................................. 275
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 278
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 278
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 279
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 279
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 280
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 281
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 281
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 282
I
I
START and STOP Conditions ......................................................................................... 313
Complete Data Transfer with a 7-Bit Address ................................................................... 314
R/S Bit in First Byte ........................................................................................................ 314
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 317
Master Single RECEIVE ................................................................................................. 318
Master Burst SEND ....................................................................................................... 319
2
2
C Block Diagram ......................................................................................................... 312
C Bus Configuration .................................................................................................... 313
®
2000 Series High-Level Block Diagram ............................................................... 26
Preliminary
2
C Bus ............................................................... 314
November 29, 2007