LM3S328-IRN20-A0T Luminary Micro, Inc., LM3S328-IRN20-A0T Datasheet - Page 22

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LM3S328-IRN20-A0T

Manufacturer Part Number
LM3S328-IRN20-A0T
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
Architectural Overview
22
ADC
I
GPIOs
Power
2
C
FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
Standard asynchronous communication bits for start, stop, and parity
False-start-bit detection
Line-break generation and detection
Single- and differential-input configurations
Eight 10-bit channels (inputs) when used as single-ended inputs
Sample rate of 500 thousand samples/second
Flexible, configurable analog-to-digital conversion
Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
Each sequence triggered by software or internal event (timers or GPIO)
Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
Interrupt generation
Master with arbitration and clock synchronization, multimaster support, and 7-bit
addressing mode
7 to 28 GPIOs, depending on configuration
5-V-tolerant input/outputs
Programmable interrupt generation as either edge-triggered or level-sensitive
Bit masking in both read and write operations through address lines
Can initiate an ADC sample sequence
Programmable control for GPIO pad configuration:
On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
Low-power options on controller: Sleep and Deep-sleep modes
Low-power options for peripherals: software controls shutdown of individual peripherals
User-enabled LDO unregulated voltage detection and automatic reset
3.3-V supply brownout detection and reporting via interrupt or reset
On-chip temperature sensor
Weak pull-up or pull-down resistors
2-mA, 4-mA, and 8-mA pad drive
Slew rate control for the 8-mA drive
Open drain enables
Digital input enables
Preliminary
April 27, 2007

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