LM3S600-IQN20-A0T Bookham Technology, Inc., LM3S600-IQN20-A0T Datasheet - Page 12
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LM3S600-IQN20-A0T
Manufacturer Part Number
LM3S600-IQN20-A0T
Description
Microcontroller
Manufacturer
Bookham Technology, Inc.
Datasheet
1.LM3S600-IQN20-A0T.pdf
(378 pages)
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Table of Contents
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
General-Purpose Timers ............................................................................................................. 157
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Watchdog Timer ........................................................................................................................... 193
Register 1:
12
GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 129
GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 130
GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 131
GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 132
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 133
GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 134
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 135
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 137
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 138
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 139
GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 140
GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 141
GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 142
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 143
GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 144
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 145
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 146
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 147
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 148
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 149
GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 150
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 151
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 152
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 153
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 154
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 155
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 156
GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 169
GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 170
GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 172
GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 174
GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 177
GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 179
GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 180
GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 181
GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 183
GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 184
GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 185
GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 186
GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 187
GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 188
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 189
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 190
GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 191
GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 192
Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 196
Preliminary
October 01, 2007
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