AN1154 STMicroelectronics, AN1154 Datasheet - Page 5

• Manufacturer Part Number: AN1154
• Description: 8031-PSD DESIGN TUTORIAL
• Manufacturer: STMicroelectronics

This is an 80C31 MCU application that has a 128K x 8 Flash memory, a 2K x 8 battery-backed SRAM, a
32K x 8 EEPROM, a real-time clock (RTC), an 8-bit analog-to-digital converter (ADC), a JTAG interface,
an EPM7064S ISP CPLD, and an analog receiver circuit (including PGA). In the discrete solution, in Figure
2, four extra IC devices are required. In the M8813F1x solution, in Figure 3, the Flash memory, EEPROM,
SRAM, CPLD, and battery backup circuitry are all combined in the M8813F1x device.
The following notes can be made regarding the discrete solution (Figure 2):
The integrated PSD design, in Figure 3, can be compared to the discrete design, in Figure 2. The memory
(U3, U4, and U6), and the battery backup circuit (U9A and U10) of Figure 2 are all incorporated into the
M8813F1x (U2) of Figure 3. Also, all of the functions handled by the CPLD (U2 of Figure 2), are
implemented in the PSD’s CPLD. The I/O pins are individually configured to match the functions
implemented in the original design.
Using JTAG, the entire M8813F1x device can be programmed. Also, the PSD JTAG pins can be
multiplexed with other I/O. These JTAG features are beyond the capabilities of the EPM7064S.
The 80C31 MCU is using external memory since internal program and data storage is not sufficient.
As a result, Port 0 and Port 1 are sacrificed for address and data.
The EPM7064SLC84-5 CPLD is needed for address decoding, control logic, implementation of a
paging/segmentation scheme for the Flash memory and EEPROM, and interfacing to the PGA and
ADC. Please refer to Appendix D for the complete design listing for U6.
The 29F010 Flash memory contains 128K x 8 bits of program memory. Notice that address lines A14-
A16 are driven by the CPLD to support the additional address space.
The A128C256 EEPROM contains 32K x 8 bits of boot memory. This allows concurrent programming
of the Flash memory. Address lines A13-A14 are driven by the CPLD to support the additional address
space.
The DP8572A RTC, programmable Real-time Clock, is used to time-stamp various data received by
the MCU.
The LH5116–2K x 8 bit SRAM is configured with battery backup protection.
The generic 8-bit ADC converts the target signal envelope into a digital value. This IC is controlled by
the CPLD.
The receiver circuit consists of a collection of components, including: a pre-amplifier, a mixer, a local
oscillator (LO), a PGA, and an envelope detector circuit. The circuit takes an RF signal from the
antenna, as input, and outputs the signal envelop.
The 7414 inverter with hysteresis (U7B) is used to provide a stable reset signal to the MCU (U1). U7A
is part of the battery backup circuit for the SRAM.
The generic OPAMP comparator is part of the battery backup circuit for the SRAM. When V
below the battery voltage, the circuit switches over to powering the SRAM from the battery.
AN1154 - APPLICATION NOTE
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