AN1154 STMicroelectronics, AN1154 Datasheet - Page 78

• Manufacturer Part Number: AN1154
• Description: 8031-PSD DESIGN TUTORIAL
• Manufacturer: STMicroelectronics

AN1154 - APPLICATION NOTE
8031 program space by the MCU writing 06h to the VM register (while still executing out of PSD
EEPROM).
Figure 62 represents the memory map after the Flash memory has been moved to the program space.
This is an intermediate step that is a result of writing to the VM register.
Next, the 8031 execution jumps from PSD EEPROM to PSD Flash memory. While executing from PSD
Flash memory, the 8031 sets a bit in the PSD page register that we call “SWAP”. The EEPROM that the
MCU booted from, during power-up, is replaced with Flash memory that contains application vectors and
code, as shown in Figure 64. The transition between the two maps of Figure 63 and Figure 64 is under
the control of the 8031 by setting the “SWAP” bit inside the PSD (defined in the PSDabel, tutor8XX.abl ,
file). Again, the state of the memory map, shown in Figure 64, is an intermediate step.
Individual bits within the 8-bit PSD page register may be used for functions other than memory page
definition. For example, in this tutorial, two of the eight PSD page register bits are use to define four
memory pages, and one of the page register bits is used as the “SWAP” bit, as described above.
Finally, while executing from the PSD Flash memory, the 8031 must write 0Ch to the VM register in the
PSD to move the PSD EEPROM from the 8031 program space to the 8031 data space. This finalizes the
memory map, as shown in Figure 65. Now, all 128 KBytes of PSD Flash memory are in the program space,
with 32 KBytes in a common area and 96 KBytes spread across three memory pages. Also, the EEPROM
is now in the data space, and is accessible from any memory page. Notice that two more PSD EEPROM
segments (EES2 and EES3) appear in Figure 65. These two segments are for general data use while the
other two EEPROM segments (EES0 and EES1) contain the 8031 power-on boot code.
Now that the system memory map looks like that of Figure 65, another feature becomes available. Besides
the mechanisms mentioned, there is one more memory mapping control bit used in this tutorial design.
This bit, “ENABLE_DATA_HALF”, is another PSD page register bit used to protect the boot code in EES0
and EES1 from inadvertent writes. At the same time, it enables the other half of the EEPROM (EES2 and
EES3) to be accessed for general data. For example, to update the boot code in EES0 and EES1 with
new code downloaded over the UART, the 8031 would leave ENABLE_DATA_HALF at logic zero,
perform the update by writing to EES0 and EES1, then set ENABLE_DATA_HALF to logic one. Now the
new boot code is inaccessible (protected while not booting), and the data half of EEPROM is accessible.
Figure 62. System Memory Map for 8031-M8813F1x, boot/download
POWER-UP (VM Register = 12h)
78/83
FFFF
C000
2000
8000
4000
0000
Execute
PROGRAM SPACE
from
here
NOTHING MAPPED
(PSEN\)
PAGE X
EES1
EES0
SYSTEM RAM & I/O
NOTHING MAPPED
PAGE 0
FS3
FS2
FS1
SYSTEM RAM & I/O
NOTHING MAPPED
PAGE 1
FS5
FS4
FS1
DATA SPACE
(RD\)
SYSTEM RAM & I/O
NOTHING MAPPED
PAGE 2
FS7
FS6
FS1
SYSTEM RAM & I/O
NOTHING MAPPED
NOTHING MAPPED
PAGE 3
FS0
FS1
FFFF
C000
8000
4000
1000
0000
ACROSS ALL
DATA PAGES
COMMON
MEMORY
AI03300