AN1212 Freescale Semiconductor / Motorola, AN1212 Datasheet - Page 13

• Manufacturer Part Number: AN1212
• Description: J1850 Multiplex Bus Communication Using the MC68HC705C8 and the SC371016 J1850 Communications Interface (JCI)
• Manufacturer: Freescale Semiconductor / Motorola

Message Filter
MOTOROLA
J1850 Multiplex Bus Communication Using the MC68HC705C8
and the SC371016 J1850 Communications Interface (JCI)
The receive (Rx) buffers are two11-byte buffers which can each store a
complete, maximum length J1850 message (without the CRC). Once the JCI
has placed a complete message in an Rx buffer, it makes this Rx buffer
available to the host while denying the host access to the other Rx buffer until
the next message has been received. Since only one of these Rx buffers can
be accessed by the host MCU at a time, to the host there appears to be only a
single Rx buffer.
This "ping-pong" action allows the JCI to store a message being received from
the MUX bus in one Rx buffer while the host MCU is retrieving a previously
received message from the other Rx buffer. Only one message can be stored
in each buffer at any one time. In either handshake interface mode, the JCI
asserts the RTS output to notify the host MCU that a complete message has
been received, and the host MCU asserts the CTS input when it is ready to
retrieve each byte. In the enhanced SPI mode, the JCI asserts the INT output
when it has received a complete message into an Rx buffer. The host MCU
then retrieves the data through a series of command bytes. The host MCU
monitors the status of each Rx buffer through the status byte.
Once the JCI has stored a message in each Rx buffer, it will ignore any further
frames being transmitted onto the MUX bus until the host MCU has either
retrieved the data from, or flushed, one of the Rx buffers. If the host MCU does
not wish to retrieve a message from an Rx buffer, it can flush the data, either
by using the FLUSH input in either handshake interface mode or with the "Flush
Current Rx FIFO" command in the enhanced SPI mode.
Due to the nature of the J1850 bus, each node must receive every frame it
transmits to ensure proper arbitration. Therefore, it is possible for the JCI to
receive, and pass back to the host, a message it has transmitted. Unless
message filtering is used to prevent this, the user’s software must be prepared
to deal with this occurrence. However, no in-frame response byte is ever
loaded into the Rx buffer or passed back to the host MCU.
For more information on the Rx and Tx buffers, refer to the J1850
Communications Interface Specification, Chapter 5: Rx/Tx FIFO’s.
In the enhanced SPI mode, the JCI can utilize a pair of 8-bit registers to filter
frames as they are received off of the MUX bus. This allows the JCI to limit the
number of messages it receives and thus the amount of host intervention
necessary. These registers are called the acceptance code register (ACR) and
the acceptance mask register (AMR).
The ACR and AMR are each loaded during initialization, and thereafter, as
each frame is being received from the MUX bus, the ACR data is compared to
the target address byte of the frame being received. Each bit in the target
address byte must match exactly each bit in the ACR for which the
corresponding bit in the AMR is set. If the unmasked bits do not match exactly,
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JCI OVERVIEW
AN1212/D
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