AN1212 Freescale Semiconductor / Motorola, AN1212 Datasheet - Page 4

• Manufacturer Part Number: AN1212
• Description: J1850 Multiplex Bus Communication Using the MC68HC705C8 and the SC371016 J1850 Communications Interface (JCI)
• Manufacturer: Freescale Semiconductor / Motorola

AN1212/D
Error Detection
Arbitration
In-Frame Response
4
J1850 Multiplex Bus Communication Using the MC68HC705C8
and the SC371016 J1850 Communications Interface (JCI)
address of the intended receivers is not know, or could change, while their
function remains the same. An example of data that would be functionally
addressed is wheel speed, which could be of interest to multiple receivers,
each with a different physical address. Functionally addressing the wheel
speed data would allow it to be transmitted to all intended receivers in a single
frame, instead of transmitting the data in a separate frame for each receiver.
Every frame transmitted onto a J1850 network contains a single byte for error
detection. Frames using the single-byte header contain a Checksum byte,
which is the simple summation of all the bytes in the frame, excluding the
delimiters and the Checksum byte itself. If the one-byte consolidated header or
the three-byte header is used, the frame must contain a cyclical redundancy
check, or CRC, byte. This byte is produced by shifting the header and data
bytes through a preset series of shift registers. The resulting byte is then
inserted in the frame following the data bytes. Any node which receives the
frame then shifts the header, data, and CRC bytes through an identical series
of shift registers, with an error free frame always producing the result $C4. In
most cases, the Checksum calculation and verification will be performed using
a software routine, while CRC bytes are generated via hardware. Any frame in
which the error detection byte does not produce the proper result is discarded
by all receivers, and any in-frame response, if required, is not transmitted.
Arbitration on the multiplex bus is accomplished in a non-destructive manner,
allowing the frame with the highest priority to be transmitted, while any
transmitters which lose arbitration simply stop transmitting and wait for an idle
bus to begin transmitting again. If multiple nodes begin to transmit at the same
time, arbitration begins with the first bit following the SOF delimiter, and
continues with each bit thereafter. Whenever a transmitting node detects a
dominant bit while transmitting a recessive bit, it loses arbitration, and
immediately stops transmitting. This is known as "bitwise" arbitration. Since a
dominant bit dominates a recessive bit (a "0" dominates a "1"), the frame with
the lowest value will have the highest priority, and will always win arbitration,
i.e., a frame with priority 000 will win arbitration over a frame with priority 001.
This method of arbitration will work regardless of how many bits of priority
encoding are contained in the frame. Frequency, messaging strategies are
utilized which ensure that all arbitration is resolve by the end of the frame
header.
The optional in-frame response, or IFR, portion of a frame follows the EOD
delimiter, and contains one of three types of information. The first type of IFR
contains a single I.D. byte from a single receiver, indicating that at least one
node received the frame. The I.D. byte is usually the physical address of the
responding node. The second type of IFR contains multiple I.D. bytes from
multiple receivers, indicating which receivers actually received the frame.
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