AN1212 Freescale Semiconductor / Motorola, AN1212 Datasheet - Page 33

• Manufacturer Part Number: AN1212
• Description: J1850 Multiplex Bus Communication Using the MC68HC705C8 and the SC371016 J1850 Communications Interface (JCI)
• Manufacturer: Freescale Semiconductor / Motorola

01D9
01DC
01DF
01E0
01E1
01E3
01E5
01E7
01E9
01EB
01ED
01EF
01F1
01F3
01F5
01F7
01F9
01FB
01FD
01FE
0201
0202
0205
0207
0208
MOTOROLA
CD0263
CD026F
9A
81
1102
B632
B70C
3D0B
2AFC
B60C
B731
B630
B70C
3D0B
1AFC
B60C
B732
1002
81
CD0233
9B
0C4206
1E42
9A
CC0216
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
************************************************************************
*****
************************************************************************
*** MC68HC705C8/JCI Data Exchange Subroutine ***
TRANSFER: bclr cs,portc
txwait1: tst
txwait2: tst
*** TRANSMIT Subroutine ***
TRANSMIT: jsr
J1850 Multiplex Bus Communication Using the MC68HC705C8
and the SC371016 J1850 Communications Interface (JCI)
Freescale Semiconductor, Inc.
For More Information On This Product,
jsr
jsr
cli
rts
lda
sta
bpl
lda
sta
lda
sta
bpl
lda
sta
bset cs,portc
rts
sei
brset txi,txcntrl,clr6 ;Has Tx completed?
bset txt,txcntrl
cli
jmp
LOADAMR
LOADACR
data
spdr
spsr
txwait1
spdr
status
command
spdr
spsr
txwait2
spdr
data
TXSTATUS
tdone
Go to: www.freescale.com
Other Subroutines
;Call subroutine to load Acceptance Mask
;Byte into Acceptance Mask Register in JCI
;Call subroutine to load Acceptance Code
;Byte into Acceptance Code Register in JCI
;Clear Host Interrupt Mask Bit
;End of JCI init subroutine
;Assert Chip Select*
;Load data byte in acc.
;Store in SPI data reg., initiating tx
;Is previous transfer complete?
;loop until done
;Load received status byte into acc.
;Store in status byte storage location
;Load command byte into acc.
;Store in SPI data reg., initiating tx
;Is previous transfer complete?
;loop until done
;Load received data byte into acc.
;Store in Data byte storage location
;Negate Chip Select*
;Return from subroutine
;Call TXSTATUS subroutine to check
;status of previously Tx’ed message
;Set I-bit to make sure "PreviousTX
;Complete" bit is not set before "Message
;to Tx" bit can be set
;Set txt bit - message to Tx
;Clear I-bit
;Jump to end of Tx subroutine routine
Code Listings
AN1212/D
******
33