DS1005 Dallas Semiconducotr, DS1005 Datasheet - Page 4

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DS1005

Manufacturer Part Number
DS1005
Description
5-Tap Silicon Delay Line
Manufacturer
Dallas Semiconducotr
Datasheet

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NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. V
4. See Test Conditions.
5. The combination of temperature variations from 25 C to 0 C or 25 C to 70 C and voltage variations
6. All tap delays tend to vary unidirectionally with temperature or voltage. For example, if TAP 1 slows
7. Pulse width and duty cycle specifications may be exceeded; however, accuracy will be application-
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
t
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
t
input pulse.
t
input pulse.
t
pulse and the 1.5V point on the leading edge of any tap output pulse.
t
pulse and the 1.5V point on the trailing edge of any tap output pulse.
WI
RISE
FALL
PLH
PHL
is greater.
from 5.0V to 4.75V or 5.0V to 5.25V may produce an additional input-to-tap delay shift of 1.5 ns or
down, all other taps will also slow down; TAP 3 can never be faster than TAP 2.
sensitive (decoupling, layout, etc.).
(Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
4%, whichever is greater.
(Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
(Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
(Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
CC
(Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
= 5V @ 25 C. Delays accurate on both rising and falling edges within 2 ns or 3%, whichever
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DS1005

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