DS1221 Dallas, DS1221 Datasheet

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DS1221

Manufacturer Part Number
DS1221
Description
Nonvolatile Controller x 4 Chip
Manufacturer
Dallas
Datasheet

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FEATURES
PIN DESCRIPTION
A, B
V
V
*
V
V
*
*
*D/Q
*Used with optional security circuit only and must be connected to ground in all other cases.
DESCRIPTION
The DS1221 Nonvolatile Controller x 4 Chip is a CMOS circuit which solves the application problem of
converting CMOS RAMs into nonvolatile memories. Incoming power is monitored for an out-of-
tolerance condition.
accomplish write protection and the battery is switched on to supply RAMs with uninterrupted power. An
optional security code prevents unauthorized users from obtaining access to the memory space. The
nonvolatile controller/decoder circuitry uses a low-leakage CMOS process which affords precise voltage
detection at extremely low battery consumption. By combining the DS1221 with up to four CMOS
memories and lithium batteries, nonvolatile operation can be achieved.
www.dalsemi.com
CE
CE0
RST
RD
WE
BAT1
BAT2
CCI
CCO
Converts CMOS RAMs into nonvolatile
memories
Data is automatically protected during power loss
2-to-4 decoder provides for up to 4 CMOS
RAMs
Provides for redundant batteries
Test battery condition on power-up
Full ±10% operating range
Unauthorized access can be prevented with
optional security feature
16-pin 0.3-inch DIP saves PC board space
Optional 16-pin SOIC surface mount package
Optional industrial temperature range of
-40°C to +85°C available
-
NOT RECOMMENDED FOR NEW DESIGNS, SEE DS1321 DATASHEET INSTEAD.
CE3
- Address Inputs
- Chip Enable Input
- Chip Enable Outputs
- + Battery 1
- + Battery 2
- Reset
- +5V Supply
- RAM Supply
- Read Inpu
- Write Input
- Data Input/Output
When such a condition is detected, the chip enable outputs are inhibited to
1 of 8
Nonvolatile Controller x 4 Chip
PIN ASSIGNMENT
VBAT1
VCCO
*RST
GND
*WE
VBAT1
*RD
DS1221 16-Pin DIP (300-mil)
See Mech. Drawings Section
DS1221 16-Pin SOIC (300-mil)
VCCO
See Mech. Drawings Section
*RST
GND
*WE
*RD
A
B
A
B
2
3
4
5
6
7
8
1
1
2
3
4
6
5
7
8
16
15
14
13
12
10
11
16
15
14
13
12
10
11
9
9
VCCI
VBAT2
CE
CE0
CE1
CE2
CE3
*D/Q
VCCI
VBAT2
CE
CE2
CE3
CE0
CE1
*D/Q
DS1221
111899

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DS1221 Summary of contents

Page 1

... DESCRIPTION The DS1221 Nonvolatile Controller x 4 Chip is a CMOS circuit which solves the application problem of converting CMOS RAMs into nonvolatile memories. Incoming power is monitored for an out-of- tolerance condition. ...

Page 2

... During nominal supply conditions the chip enable outputs follow the logic of a 2-to-4 decoder. The fifth function the DS1221 performs is to check battery status to warn of potential data loss. Each time that V power is restored the battery voltage is checked with a precision comparator. If the connected battery voltage is less than 2 volts, the second memory cycle is inhibited ...

Page 3

... TYPICAL APPLICATION Figure 2 SECURITY SEQUENCE Figure 3 OUTPUT LOAD Figure DS1221 ...

Page 4

... CCI V V -0.2 CCO CC I CCO1 4.25 4.37 CCTP SYMBOL MIN TYP V -0.2 V OHL CC V -0.2 BAT I BAT I CCO2 DS1221 ( MAX UNITS NOTES 4.5 to 5.5V) CC MAX UNITS NOTES +1.0 µA +1.0 µ 4.0 ...

Page 5

... I is the maximum average load which the DS1221 can supply to the memories. CCO1 5. Measured with a load as shown in Figure the maximum average load current which the DS1221 can supply to the memories in the CCO2 battery back-up mode. 7. Chip enable outputs - CE0 8 ...

Page 6

... For each of the 64 read cycles, 1 bit of the user-defined read only register is driven onto the DQ line. This phase also requires that the 64 read cycles be consecutive. The data being read from the read only register can be used by software to determine if the DS1221 will be permitted to be used with that particular system. After the 64 subsequent memory cycles will be passed through and will become actual memory accesses based upon address inputs ...

Page 7

... POWER-DOWN Figure 5 POWER-UP Figure DS1221 ...

Page 8

... READ CYCLE TO SECURITY OPTION Figure 7 WRITE CYCLE TO SECURITY OPTION Figure 8 NOTES and t are functions of the first occurring edge function of the latter occurring edge of WR RESET FOR SECURITY OPTION Figure DS1221 ...

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