DS1222 Dallas, DS1222 Datasheet - Page 2

• Manufacturer Part Number: DS1222
• Description: BankSwitch Chip
• Manufacturer: Dallas

OPERATION - BANK SWITCHING
Initially, on power-up all four bank select outputs are low and the chip enable output (
(Note: the power fail input [
switching is achieved by matching a predefined pattern stored within the DS1222 with a 16-bit sequence
received on four address inputs. Prior to entering the 16-bit pattern, which sets the bank switch, a read
cycle of 1111 on address inputs AW through AZ should be executed to guarantee that pattern entry starts
with bit 0. Each set of address inputs is clocked into the DS1222 when
must be consecutive read cycles. The first eleven cycles must match the exact bit pattern as shown in
Table 1. The last five cycles must match the exact bit pattern as shown for addresses AX, AY, and AZ.
However, address line AW defines the bank number to be enabled as per Table 2.
Switching to a selected bank of memory occurs on the rising edge of
and a match has been established. After bank selection
propagation delay of 15 ns. The bank selected is determined by the levels set on Bank Select 1 through
Bank Select 4 as per Table 2. These levels are held constant for all memory cycles until a new memory
bank is selected.
ADDRESS BIT SEQUENCE Table 1
BANK SELECT CONTROL Table 2
*
CEO
*Banks Off
Selected
Bank 10
Bank 11
Bank 12
Bank 13
Bank 14
Bank 15
ADDRESS
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
Bank 8
Bank 9
INPUTS
Bank
A
A
A
A
=V
W
X
Y
Z
IH
independent of
11
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
12
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CEI
2
1
0
1
0
A
P
W
I F
Bit Sequence
] must be low prior to power-up to assure proper initialization.) Bank
3
0
1
0
1
13
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
4
0
1
0
1
BIT SEQUENCE
5
0
1
0
1
14
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
2 of 4
6
1
0
1
0
7
1
0
1
0
15
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CEO
8
0
1
0
1
always follows
High
High
High
High
High
High
High
High
BS1
Low
Low
Low
Low
Low
Low
Low
Low
Low
9
1
0
1
0
CEI
CEI
10
when the last set of bits is input
0
1
0
1
is driven low. All 16 inputs
High
High
High
High
High
High
High
High
Outputs
Low
Low
Low
Low
Low
Low
Low
Low
Low
BS2
11
x
0
1
0
CEI
12
x
0
1
0
CEO
with a maximum
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
BS3
13
0
1
0
x
) is held high.
X See Table 2
14
x
1
0
1
High
High
High
High
High
High
High
High
BS4
Low
Low
Low
Low
Low
Low
Low
Low
Low
DS1222
15
1
0
1
x