DS1225Y Dallas, DS1225Y Datasheet - Page 6

• Manufacturer Part Number: DS1225Y
• Description: 64k Nonvolatile SRAM
• Manufacturer: Dallas

POWER–DOWN/POWER–UP CONDITION
POWER–DOWN/POWER–UP TIMING
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high for a read cycle.
2. OE = V
3. t
4. t
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
DS1225Y
021998 6/8
SEE NOTE 11
PARAMETER
CE at V
V
V
CE at V
PARAMETER
Expected Data Retention Time
LEAKAGE CURRENT
I
LITHIUM CELL
L
CC
CC
SUPPLIED FROM
earlier of CE or WE going high.
buffers remain in a high impedance state during this period.
in a high impedance state during this period.
WP
DS
Slew from V
Slew from 0V to V
is measured from the earlier of CE or WE going high.
is specified as the logical AND of CE and WE. t
IH
IH
IH
before Power–Down
after Power–Up
or V
V
CE
CC
IL
TP
V
. If OE = V
3.2V
TP
to 0V
TP
t
F
t
PD
IH
during a write cycle, the output buffers remain in a high impedance state.
DATA RETENTION TIME
SYM
SYM
t
t
REC
t
WP
PD
t
DR
t
F
R
t
DR
is measured from the latter of CE or WE going low to the
MIN
100
MIN
10
0
0
MAX
MAX
t
2
REC
t
R
UNITS
UNITS
years
ms
s
s
s
(t
A
NOTES
NOTES
= 25 C)
11
9