DS17485 Dallas, DS17485 Datasheet - Page 21

• Manufacturer Part Number: DS17485
• Description: (DS17486 / DS17487) 3V/5V Real-Time Clock
• Manufacturer: Dallas

EXTENDED CONTROL REGISTERS
Two extended control registers are provided to supply controls and status information for the extended
features offered by the DS17485/DS17487. These are designated as extended control registers 4A and 4B
and are located in register bank 1, locations 04AH and 04BH, respectively. The functions of the bits
within these registers are described as follows.
EXTENDED CONTROL REGISTER 4A
VRT2 – Valid RAM and Time 2. A read-only status bit. When VRT2 = 0, the RTC and RAM data are
questionable and indicates that the lithium energy source connected to the V
exhausted and should be replaced. This bit indicates the status of the V
INCR – Increment in Progress Status. This bit is set to a 1 when an increment to the time/date registers
is in progress and the alarm checks are being made. INCR is set to a 1 at 122µs before the update cycle
starts and is cleared to 0 at the end of each update cycle.
BME – Burst Mode Enable. The burst mode enable bit allows the extended user RAM address registers
to automatically increment for consecutive reads and writes. When BME is set to a logic 1, the automatic
incrementing is enabled and when BME is set to a logic 0, the automatic incrementing is disabled.
PAB – Power-Active Bar-Control. When this bit is 0, the
bit is 1, the
either WF and WIE = 1 or KF and KSE = 1, the PAB bit is cleared to 0.
RF – Ram Clear Flag. This bit is set to a logic 1 when a high-to-low transition occurs on the
input if RCE = 1. The RF bit is cleared by writing it to a logic 0. This bit can also be written to a logic 1
to force an interrupt condition.
WF – Wake-Up Alarm Flag. This bit is set to 1 when a wake-up alarm condition occurs or when the
user writes it to a 1. WF is cleared by writing it to a 0.
KF – Kickstart Flag. This bit is set to a 1 when a kickstart condition occurs or when the user writes it to
a 1. This bit is cleared by writing it to a logic 0.
*Reserved bits. These bits are reserved for future use by Dallas Semiconductor. They can be read and
written, but have no affect on operation.
MSB
VRT2
BIT 7
PWR
BIT 6
INCR
pin is in the high-impedance state. This bit can be written to a logic 1 or 0 by the user. If
BIT 5
BME
BIT 4
*
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BIT 3
PAB
PWR
pin is in the active low state. When this
BIT 2
BAUX
RF
input.
BIT 1
BAUX
WF
input has been
BIT 0
KF
LSB
RCLR