DS2016 Dallas Semiconducotr, DS2016 Datasheet - Page 7

• Manufacturer Part Number: DS2016
• Description: 2k x 8 3V/5V Operation Static RAM
• Manufacturer: Dallas Semiconducotr

TIMING DIAGRAM: DATA RETENTION - POWER-UP, POWER-DOWN Figure 1
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
DC TEST CONDITIONS
Outputs Open
All voltages are referenced to ground.
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0V - 3.0V
Timing Measurement Reference Levels
Input Pulse Rise and Fall Times: 5 ns
SEE NOTE 8
state.
t
going low to the earlier of
t
If the
output buffers remain in a high impedance state.
If the
buffers remain in a high impedance state.
If
transition, the output buffers remain in a high impedance state.
If the V
2.7V, I
The DS2016 maintains full operation from 5.5V to 2.7V. The electrical characteristics tables show
two tested and guaranteed points of operation. For operation between 4.5V and 3.5 volts, use the
composite worst case characteristics from both 5V and 3V operation for design purposes.
OE
WE
WP
DH
Input: 1.5V
Output: 1.5V
WE
and t
is specified as the logical AND of
is high for read cycles.
= V
CE
CCS1
CE
is low or the
IH
IH
DS
high transition occurs prior to or simultaneously with the
or V
level of CE is 2.0V during the period that V
are measured from the earlier of
low transition occurs simultaneously with or later than the
current flows.
IL
. If
OE
WE
= V
CE
low transition occurs prior to or simultaneously with the
IH
or
during write cycle, the output buffers remain in a high impedance
WE
going high.
CE
7 of 9
and
CE
WE
or
WE
. t
WP
going high.
is measured from the latter of
CC
voltage is going down from 4.5V to
WE
high transition, the output
WE
low transition, the
CE
CE
or
DS2016
WE
low