DS26502 Maxim Integrated Products, DS26502 Datasheet - Page 42

• Manufacturer Part Number: DS26502
• Description: T1/E1/J1/64KCC BITS Element
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
Bit 0: Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS)
Bits 1 and 5: Unused, must be set = 0 for proper operation.
Bit 2: Transmit-Side D4 Yellow Alarm Select (TD4YM)
Bit 3: F-Bit Corruption Type 1 (FBCT1). A low-to-high transition of this bit causes the next three consecutive Ft (D4
framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of frame (loss of
synchronization).
Bit 4: F-Bit Corruption Type 2 (FBCT2). Setting this bit high enables the corruption of one Ft (D4 framing mode) or FPS
(ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set.
Bit 6: Transmit Fs-Bit Insertion Enable (TFSE). Only set this bit to a 1 in D4 framing applications. Must be set to 1 to
source the Fs pattern from the TFDL register. In all other modes this bit must be set = 0.
Bit 7: Transmit B8ZS Enable (TB8ZS)
0 = no stuffing occurs
1 = bit 7 forced to a 1 in channels with all 0s
0 = 0s in bit 2 of all channels
1 = a 1 in the S-bit position of frame 12
0 = Fs-bit insertion disabled
1 = Fs-bit insertion enabled
0 = B8ZS disabled
1 = B8ZS enabled
TB8ZS
PIN 55
HBE
7
0
TFSE
T1TCR2
T1 Transmit Control Register 2
06h
6
1
1
—
5
0
0
FBCT2
4
0
0
42 of 124
www.DataSheet4U.com
FBCT1
3
0
0
TD4YM
2
0
0
DS26502 T1/E1/J1/64KCC BITS Element
—
1
0
0
TB7ZS
0
0
0