DS2760 Dallas Semiconducotr, DS2760 Datasheet
DS2760
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DS2760 Summary of contents
Page 1
... SNS Probe – Do not connect VSS Probe – Do not connect PRELIMINARY DS2760 VIN PLS CC VIN VDD VDD PIO PIO VSS SNS NC NC Probe Probe VSS VSS SNS VSS VSS PS DQ IS2 IS1 PS 9 IS1 DS2760 Flip-Chip Packaging 092000 ...
Page 2
... This low-power device integrates precise temperature, voltage, and current measurement, nonvolatile data storage, and Li-Ion protection into the small footprint of either a TSSOP package or flip-chip. The DS2760 is a key component in applications including remaining capacity estimation, safety monitoring, and battery-specific data storage. ...
Page 3
... IS2 PLS PS SNS 1-WIRE AND VOLTAGE REFERENCE MUX ADC internal sense resistor configuration only 25 m IS2 IS1 REGISTERS AND USER MEMORY LOCKABLE EEPROM SRAM TEMPERATURE VOLTAGE CURRENT TIMEBASE ACCUM. CURRENT STATUS / CONTROL LI-ION PROTECTION chip ground DS2760 PIO CC DC VSS ...
Page 4
... VSS and SNS. IS1 Current Sense Input. This pin is internally connected to VSS through a 4.7 k resistor. Connect a 0.1 F capacitor between IS1 and IS2 to complete a low-pass input filter. IS2 Current Sense Input. This pin is internally connected to SNS through a 4.7 k resistor DS2760 ...
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... SENSINT 102 1 k DS2760 CC VIN PLS VDD DC PIO 150 SNS VSS SNS VSS 150 SNS VSS DQ PS IS2 IS1 104 150 1 k 104 (1) R SENS DS2760 SNS ( SENSINT KS IS2 voltage sense DS2760 BAT+ BAT- VSS KS IS1 ...
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... TST Overvoltage. If the voltage of the cell exceeds overvoltage threshold V overvoltage delay t , the DS2760 shuts off the external charge FET and sets the OV flag in the OVD Protection Register. When the cell voltage falls below charge enable threshold V charge FET back on (unless another protection condition prevents it). Discharging remains enabled during overvoltage ...
Page 7
... Undervoltage. If the voltage of the cell drops below undervoltage threshold V undervoltage delay t , the DS2760 shuts off the charge and discharge FETs, sets the UV flag in the UVD Protection Register, and enters Sleep Mode. Overcurrent, Charge Direction. The voltage difference between the IS1 pin and the IS2 pin (V – ...
Page 8
... Mode) CURRENT MEASUREMENT In the Active Mode of operation, the DS2760 continually measures the current flow into and out of the battery by measuring the voltage drop across a current sense resistor. The DS2760 is available in two configurations: (1) internal 25 m current sense resistor, and (2) external user-selectable sense resistor. In ...
Page 9
... CURRENT OFFSET BIAS – Figure 6 VOLTAGE MEASUREMENT The DS2760 continually measures the voltage between pins VIN and VSS over a range 5-volts. The resulting data is placed in the Voltage Register in two’s-complement format with a resolution of 4.88 mV. Voltages above the maximum register value are reported as the maximum value. The Voltage Register format is shown in Figure 7. VOLTAGE REGISTER FORMAT – ...
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... PIO bit disables the output driver, allowing the PIO pin to be pulled high or used as an input. To sense the value on the PIO pin, read the PIO bit. The DS2760 turns off the PIO output driver when in enters Sleep Mode or when DQ is low for more than 2 seconds, regardless of the state of the PMOD bit. ...
Page 11
... UV – Undervoltage Flag. When set to 1, this bit indicates the battery pack has experienced an undervoltage condition. This bit must be reset by the host system. Description Address 00 bit 5 bit 4 bit 3 COC DOC Read/Write R/W R R/W R R/W R R/W* R/W* R/W bit 2 bit 1 bit DS2760 ...
Page 12
... X X PMOD – Sleep Mode Enable. A value this bit enables the DS2760 to enter Sleep Mode when the DQ line goes low for greater than 2 seconds and leave Sleep Mode when the DQ line goes high. A value of 0 disables DQ-related transitions into and out of Sleep Mode. This bit is read-only. The desired default value should be set in bit 5 of address 31h. RNAOP – ...
Page 13
... A 0 signifies that this device is not the master. X – Reserved bits. Address 07 bit 5 bit 4 bit Address 08 bit 5 bit 4 bit 3 MSTR bit 2 bit 1 bit 0 X BL1 BL0 bit 2 bit 1 bit DS2760 ...
Page 14
... Each DS2760 has a unique, factory-programmed 1-Wire net address which is 64 bits in length. The first 8 bits are the 1-Wire family code (30h for DS2760). The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits (see Figure 13). The 64-bit net address and the 1-Wire I/O circuitry built into the device enable the DS2760 to communicate via the 1-Wire protocol detailed in the 1-Wire Bus System section of this datasheet ...
Page 15
... To facilitate this, each device attached to the 1-Wire bus must connect to the bus with open-drain or tri-state output drivers. The DS2760 used an open-drain output driver as part of the bi-directional interface circuitry shown in Figure 15 bi-directional pin is not available on the bus master, separate output and input pins can be tied together ...
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... The term power control refers to the ability of the DS2760 to control the flow of power into or out the battery pack using control pins DC and CC . The SWAP command is issued followed by the Net Address ...
Page 17
... LSb of the data at address XX+1 is available to be read immediately after the MSb of the data at address XX. If the bus master continues to read beyond address FFh, the DS2760 outputs logic 1 until a Reset Pulse occurs. Addresses labeled “Reserved” in the Memory Map contain undefined data. The Read Data command may be terminated by the bus master with a Reset Pulse at any bit boundary ...
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... Permanently locks the Lock block of EEPROM containing address XX Command Bus State After Protocol Command Protocol 69h, XX Master Rx 6Ch, XX Master Tx 48h, XX Master Reset B8h, XX Master Reset 6Ah, XX Master Reset DS2760 Bus Data up to 256 bytes of data up to 256 bytes of data none none none ...
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... MASTER Tx NET ADDRESS COMMAND NO F0h NO SEARCH YES DS2760 Tx BIT 0 DS2760 Tx BIT 0 MASTER Tx BIT BIT 0 MATCH ? YES DS2760 Tx BIT 1 DS2760 Tx BIT 1 MASTER Tx BIT BIT 1 MATCH ? YES DS2760 Tx BIT 63 DS2760 Tx BIT 63 MASTER Tx BIT 63 FALLING EDGE OF DQ DS2760 to Sleep Mode AAh NO ...
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... DS2760 to present valid data. The bus master can then sample the data t the read time slot. By the end of the read time slot, the DS2760 releases the bus line and allows pulled high by the external pull-up resistor. All read time slots must be t ...
Page 21
... Both bus master and DS2760 active low t SWL t SWOFF WRITE 1 SLOT t SLOT t LOW1 DS2760 Sample Window MIN TYP MAX READ 1 SLOT t SLOT Master Sample Window DS2760 active low Resistor pullup t SWON DS2760 PACK+ PACK– PACK+ PACK– ...
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... See J-STD-020A Specification VDD TYP MAX UNITS 2.5 5.5 V -0.3 5.5 V VDD MIN TYP MAX UNITS 1.5 V -0.2V V 0.4 V 0.2 V -0. 0.4 V 0.4 V 500 4000 ppm sec DS2760 5.5V) NOTES 1 1 5.5V) NOTES ...
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... V 4.05 4. 2.5 2 1 100 150 SC t 0.8 1 OVD t 90 100 UVD OCD t 80 100 SCD V 0.5 1 TST DS2760 VDD 5.5V) MAX UNITS NOTES 4.400 V 1,2 4.325 1,4 200 mV 1 1.2 sec 110 120 s 1 ...
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... 2.5V SYMBOL MIN TYP t 2 EEC N 25000 EEC VDD MAX UNITS LSB 5 %V reading LSB 1 %I reading mAhr µVhr VDD MAX UNITS 10 ms cycles DS2760 5.5V) NOTES 5.5V) NOTES 11 ...
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... Requires in-system calibration by user. 9. This spec excludes the effects of temperature on the sense resistor. The DS2760 compensates for the internal sense resistor’s temperature coefficient of 4000 ppm accuracy of 500 ppm/ C. The DS2760 does not attempt to compensate for the characteristics of an external sense resistor. Error terms arising from the use of an external sense resistor should be taken into account when calculating total current measurement error ...