AN1902 Freescale Semiconductor / Motorola, AN1902 Datasheet - Page 25

• Manufacturer Part Number: AN1902
• Description: Quad Flat Pack No-Lead (QFN)
• Manufacturer: Freescale Semiconductor / Motorola

8.0 PACKAGE THERMAL RESISTANCES
MOTOROLA
7.3 Increasing SJR for High Reliability Applications
The QFN package is one of the promising candidates in replacing bigger leaded pack-
ages. This package is able to accommodate a larger die size for the same package
size. On the flip side, leaded packages have among the longest SJR life of all pack-
ages due to its lead shape and its ability to reduce the stress from coefficient of ther-
mal expansion mismatch.
A majority of the studies for SJR in high reliability applications have been conducted
with 7x7mm and 9x9mm 0.65mm pitch packages. Several iterations of board and
stencil designs were required to meet SJR of greater than 2000 TFF for these two
package sizes. For high reliability applications, Motorola recommends evaluating the
QFN package on a case by case basis. This applies to all lead count and package
sizes. The TTF values provided in
many factors. If repeatability is taken into account, the typical TTF values would be
lower than the values shown in
The thermal performance of the QFN package is characterized using two thermal
board types and three boundary conditions. Junction-to-ambient thermal resistance
(Theta-JA or R
measures the conduction of heat from the junction (hottest temperature on die) to the
environment near the package. The heat that is generated on the die surface reaches
the immediate environment along two paths: (1) convection and radiation off the
exposed surface of the package and (2) conduction into and through the test board
followed by convection and radiation off the exposed board surfaces. R
the thermal performance of the package in a low conductivity test board (single signal
layer – 1s) in a natural convection environment. The 1s test board is designed per
JEDEC EIA/JESD51-3 [8] and JEDEC EIA/JESD51-5 [9]. Another thermal resistance
that is commonly reported is Theta-JMA or R
and two internal planes (2s2p). The 2s2p test board is designed per JEDEC
EIA/JESD51-5 [9] and JEDEC EIA/JESD51-7 [10]. R
thermal performance of the QFN package in a customer’s application. R
mate the thermal performance of the QFN package when it is mounted in two distinct
configurations: (1) a board with no internal thermal planes (i.e. low conductivity board)
or (2) when a multi-layer board is tightly populated with similar components. R
provides the thermal performance of the QFN when there are no nearby components
dissipating significant amounts of heat on a multi-layer board. Junction-to-board ther-
mal resistance (Theta-JB or R
the QFN package. R
tion and the board. The board temperature is taken 1 mm from the package on a
board trace located on the top surface of the board. Another thermal resistance that is
provided is junction-to-case thermal resistance (Theta-JC or R
defined at the exposed pad surface. R
Freescale Semiconductor, Inc.
For More Information On This Product,
Quad Flat Pack No-Lead (QFN)
θJA
Go to: www.freescale.com
per JEDEC EIA/JESD51-2 [7]) is a one-dimensional value that
θJB
measures the horizontal spreading of heat between the junc-
θJB
Table 7
per JEDEC EIA/JESD51-8 [11]) is also provided for
Table 7
θJC
and
can be used to estimate the thermal perfor-
and
Table
θJMA
Table 8
on a board with two signal layers
8.
θJA
are highly dependent upon
and R
θJC
θJMA
). The case is
help bound the
θJA
θJA
measures
AN1902/D
helps esti-
θJMA
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