AN2007 Motorola / Freescale Semiconductor, AN2007 Datasheet - Page 4

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AN2007

Manufacturer Part Number
AN2007
Description
Evaluating ColdFire in a 68K Target System: MC68340 Gateway Reference Design
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
MC68340 PGA–MCF5206FT, Gateway Reference Design
A key feature required for debugging a microprocessor system is memory. This allows the designer to
download and run code. The ColdFire MCF5206 microprocessor has 512 bytes of on-chip Static RAM
(SRAM) and a DRAM control module built onto the silicon from which external memory can be
“gluelessly” interfaced. The DRAM controller offers the designer a clear cost saving by reducing the
component count of the system. This module also provides the flexibility to interface to multiple memory
configurations.
In addition to requiring DRAM or SRAM memory for debugging software, many designers require
non-volatile storage in the form of FLASH memory to store boot code or data that has been collected by the
system. Data or code stored in FLASH memory can be accessed, modified or erased via the BDM port.
With this in mind, the MC68340 to MCF5206 Gateway Reference Module was designed with 1 Mbyte of
EDO DRAM, 1 Mbyte FLASH ROM, 1 additional 8-bit I/O port and a two channel DMA controller. It
consists of two boards, an interconnect board that will connect to the 68K target and a microprocessor /
memory board which contains the ColdFire device. This second board provides additional hardware
performing many tasks such as control processing from external hardware, pulling active low control signals
to a high logic level and decoupling all power supplies to suppress noise. Given the modules incorporated
into the design, the reference module can be considered a self-contained ColdFire sub-system.
1.2 MC68340 PGA–MCF5206FT, Gateway Reference
Design
1.2.1 MCF5206 CPU, DMA Controller, RESET and Clock
Circuit
Figure 4 shows the circuit diagram of the 2-channel DMA controller with the MCF5206 microprocessor.
The logic for the DMA controller was implemented using a Motorola MC92310CE ASIC specifically
designed for this function
4
MC68340 Gateway Reference Design

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