AN2007 Motorola / Freescale Semiconductor, AN2007 Datasheet - Page 8

• Manufacturer Part Number: AN2007
• Description: Evaluating ColdFire in a 68K Target System: MC68340 Gateway Reference Design
• Manufacturer: Motorola / Freescale Semiconductor

1.3 DRAM & FLASH Memory
Figure 11 shows the connections of the on-board 1 Mbyte Fujitsu FLASH ROM (MBM29F800T) and the
two blocks of EDO DRAM giving 1Mbyte of available RAM memory (MCM518160BT60).
The MCF5206 Microprocessor is connected directly to the EDO DRAM using the Column Address Strobes
(CAS). CAS0, 1 are connected to the lower pictured chip and CAS 2 and 3 are connected to the upper chip
in the diagram. The row address strobe 0 (RAS0) is connected to the RAS input on both chips, as is the
DRAMW signal.
By connecting the RAS and CAS signals in this way to the two blocks of EDO DRAM, 1 Mbyte of EDO
DRAM can be accessed using a 32-bit wide data bus.
The logic created by PAL U9 is used to drive the 1Mbyte FLASH ROM. Pull-up resistors (10K) are required
for stable FLASH operation and these are connected to /BYTE and RY/BY active low pins on the chip. The
pull-up resistor attached to the /BYTE pin on the FLASH device sets the operation to run in 16-bit data bus
mode as opposed to the active low 8-bit setting.
Both the two EDO DRAM memory chips and the FLASH ROM chip are connected onto the main data
(D0..31) and address bus (A1..21) of the MCF5206 Microprocessor.
1.4 Test Points, Decoupling and Pull-Up Resistors
Figure 10 details the key signals that can be accessed through test access points positioned on the module
to aid debugging, particularly when connected to MC68340 hardware. The signals that are accessible are
/TS, /AS, /DS, /DTACK, /TA, CLKOUT and R/W.
Also listed on this schematic page are the necessary signals that must be pulled-up to a high logic level to
avoid false signalling. Each signal that requires a pull-up is tied to 5V using a 4.7Kohm resistor.
Jumper 5 on the schematic multiplexes BDM debug operation and JTAG operation of the MCF5206
Microprocessor. If the jumper is placed in position 2 / 3, BDM operation will be selected. Similarly, if the
jumper is placed in position 1 / 2, JTAG operation will be selected.
1.5 Considerations for Implementing a MCF5206e
In many ways, the implementation of a MC68340 – MCF5206e Gateway board is much easier and offers
higher performance due to the enhanced features of this device.
Instantly, the MCF5206 Gateway reference design can be simplified by removing the circuitry surrounding
the MC92310CE two channel DMA chip.
DRAM & FLASH Memory
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Gateway Board
No need for MC92310CE ASIC implementing the logic for a 2 channel DMA. The MCF5206e
Microprocessor has a 2 channel DMA controller on-chip.
Performance improvement with the MCF5206e over the MCF5206 – 50MIPS as opposed to
17MIPS!
Maximum frequency improvement, MCF5206 has a maximum frequency of 33MHz and the
MCF5206e has a maximum frequency rating of 54MHz.
Total pin compatibility of the 160 pin MCF5206e and the MCF5206 Microprocessors.
MCF5206e Microprocessor can handle 5V input signals, while operating from a +3.3V power
supply.
MC68340 Gateway Reference Design