AN2007 Motorola / Freescale Semiconductor, AN2007 Datasheet - Page 7

• Manufacturer Part Number: AN2007
• Description: Evaluating ColdFire in a 68K Target System: MC68340 Gateway Reference Design
• Manufacturer: Motorola / Freescale Semiconductor

MC68340 PGA–MCF5206FT, Gateway Reference Design
The initial target for this Gateway design was a MC68340 in a PGA package. With the use of an adapter,
this reference design has also been used to target a MC68340 in a PQFP package in a customers target
system.
1.2.4 PAL Logic for Bus Arbitration & FLASH Control
As previously discussed, the Gateway reference design has FLASH memory on the board. Additional logic
is required to interface the FLASH memory with the MCF5206. This is achieved by coding one PAL, U9,
and connecting it as shown in Figure 6. PAL U8 is used to decode DMA signals and arbitrate the bus. The
PAL equations for U8 and U9 are shown in Appendices A and B, respectively.
1.2.5 PAL Control Equations–U8
A bus arbiter is required to arbitrate between the buses of the MC68340, MCF5206 and the DMA controller.
PAL U8 performs this function.
All of the logic equations assume that the system is not held in RESET and that the 68340 target hardware
has the highest priority when arbitrating for the bus.
For the target hardware to assume control of the bus, BR from target hardware and BG to the DMA must be
asserted.
For the MCF5206 to assume control of the bus the following conditions must be met:
Bus grant signal from the DMA controller, bus request signal from the MCF5206 and bus grant to MCF5206
must be asserted. The bus request from the MC68340 and bus grant to the 68340 must not be asserted.
A bus request signal for the DMA is created by OR’ing the two bus request signals, (MCF5206 and
MC68340 bus request signals) together.
DMA is requested from the MC68340 hardware by the data request signals (either DREQ1 or DREQ2).
When arbitrated off the bus the MCF5206 monitors the SIZ pins to determine the physical size of the
required data transfer. The SIZx pins are driven into the correct configuration by the PAL U8.
Dynamic Bus sizing is not supported by ColdFire. The size of the data transfer is determined by the
initialisation code. This code configures both chip select data size and address range as well as
DRAM data size and address range.
Appendix A illustrates all of the relevant control equations and simulation setups for coding PAL U8.
1.2.6 PAL Control Equations–U9
The 8Mbit Fujitsu MBM29F800 Flash device on the Gateway module is activated using chip select 0 (CS0)
from the MCF5206. Jumper J4 multiplexes CS0 between the FLASH (CS0_ON) and the target hardware
(CS0_OFF).
The control signals for the FLASH device are generated by PAL U9. These control signals consist of Write
Enable (F_WE), Reset (F_RESET), Output Enable (F_OE) and Data Transfer Acknowledge (DTACK).
The generation of the DTACK signal for target hardware FLASH read/write accesses is slightly more
complex than the other control signals. Two registered signals called COUNT0 and COUNT1 are created.
These signals allow two wait states to be incorporated into the system for CS0_OFF and CS1. DTACK is
generated from these signals.
Appendix B illustrates the corresponding set of PAL control equations for generating the FLASH and
DTACK control signals.
MC68340 Gateway Reference Design
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