CY22150ZC Cypress Semiconductor, CY22150ZC Datasheet
CY22150ZC
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CY22150ZC Summary of contents
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... XOUT Serial SDAT Programming SCLK Interface Pin Configuration Cypress Semiconductor Corporation Document #: 38-07104 Rev. *F times, reducing inventory of custom parts and providing an easy method for upgrading existing designs. • The CY22150 can be programmed at the package level. In-house programming of samples and prototype quantities is available using the CY3672 FTG Devel- opment Kit. Production quantities are available through Cypress’ ...
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Part Number Outputs Input Frequency Range CY22150FC 6 8 MHz–30 MHz (external crystal) 1 MHz–133 MHz (driven clock) CY22150FI 6 8 MHz–30 MHz (external crystal) 1 MHz–133 MHz (driven clock) Pin Definitions Pin Name Pin Number Pin Description XIN 1 ...
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DIV1N [OCH] DIV1SRC [OCH] Qtotal REF PFD (Q+2) [42H] DIV2SRC [47H] DIV2N [47H] CLKOE [09H] Default Start-up Condition for the CY22150 The default (programmed) condition of the device is generally set by the distributor who programs the device using a ...
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CapLoad setting during crystal start-up. Bits 3 and 4 of register 12H control the input crystal oscillator gain setting. Bit 4 is the MSB of the setting, and bit 3 is the LSB. The setting is programmed ...
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Input Load Capacitors Input load capacitors allow the user to set the load capacitance of the CY22150 to match the input load capacitance from a crystal. The value of the input load capacitors is determined by 8 bits in a ...
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Table 6. P Counter Register Definition Address D7 D6 40H 1 1 41H PB(7) PB(6) 42H PO Q(6) Table 7. P Counter Register Definition Address D7 D6 40H 1 1 41H PB(7) PB(6) 42H PO Q(6) Table 8. PLL Post ...
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Table 11. CLKSRC2 CLKSRC1 CLKSRC0 Table 12. Address D7 D6 44H CLKSRC2 CLKSRC1 for LCLK1 for ...
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Slave SDAT Write ACK R Multiple 7-bit Contiguous Device Registers Address Start Signal 1-bit 1-bit Slave SDAT Read ACK R Multiple 7-bit Contiguous Device Registers Address Start Signal SDAT + START DA6 DA5DA0 R/W ...
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Applications Controlling Jitter Jitter is defined in many ways including: phase noise, long-term jitter, cycle to cycle jitter, period jitter, absolute jitter, and deterministic. These jitter terms are usually given in terms of rms, peak to peak the ...
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Table 14. Absolute Maximum Conditions Parameter V Supply Voltage DD V I/O Supply Voltage DDL T Storage Temperature S T Junction Temperature J Package Power Dissipation – Commercial Temp Package Power Dissipation – Industrial Temp Digital Inputs Digital Outputs referred ...
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... Systems: Causes, Effects, and Solutions,” available at http://wwww.cypress.com/clock/appnotes.html, or contact your local Cypress field appli- cations engineer). 10. The CY22150ZC-xxx and CY22150ZI-xxx are factory programmed configurations. Factory programming is available for high-volume design opportunities of 100Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative. ...
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... Document #: 38-07104 Rev. *F © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...
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Document History Page Document Title: CY22150 One-PLL General-Purpose Flash-Programmable and 2-Wire Serially-Programmable Clock Generator Document Number: 38-07104 ECN Issue REV. NO. Date ** 107498 08/08/01 *A 110043 02/06/02 *B 113514 05/01/02 *C 121868 12/14/02 *D 125453 05/19/03 *E 242808 See ...