CY22150ZC Cypress Semiconductor, CY22150ZC Datasheet - Page 4

• Manufacturer Part Number: CY22150ZC
• Description: One-PLL General-Purpose Flash-Programmable and 2-Wire Serially Programmable Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07104 Rev. *F
manufacturer), and the CapLoad setting during crystal
start-up.
Bits 3 and 4 of register 12H control the input crystal oscillator
gain setting. Bit 4 is the MSB of the setting, and bit 3 is the
LSB. The setting is programmed according to Table 2. All other
Table 1. Summary Table – CY22150 Programmable Registers
Table 2. Programmable Crystal Input Oscillator Gain Settings
Table 3. Bit Locations and Values
Table 4. Programmable External Reference Input Oscillator Drive Settings
Crystal Input
Frequency
Register
Reference Frequency
Drive Setting
Address
OCH
09H
12H
13H
40H
41H
42H
44H
45H
46H
47H
12H
CLKOE control
DIV1SRC mux and
DIV1N divider
Input crystal oscillator
drive control
Input load capacitor
control
Charge Pump and PB
counter
PO counter, Q
counter
Crosspoint switch
matrix control
DIV2SRC mux and
DIV2N divider
Effective Load Capacitance
Description
Cap Register Settings
D7
0
Crystal ESR
15 – 20 MHz
20 – 25 MHz
25 – 30 MHz
8 – 15 MHz
(CapLoad)
D6
CLKSRC2
CLKSRC0
CLKSRC1
for LCLK1
for LCLK3
0
DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0)
DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0)
CapLoad
for CLK6
PB(7)
PO
D7
(7)
1 – 25 MHz
0
0
1
00
CLKSRC1
CLKSRC2
CLKSRC0
for LCLK1
for LCLK4
CapLoad
for CLK6
D5
PB(6)
1
Q(6)
D6
(6)
0
0
1
30Ω
00
01
01
10
6 pF to 12 pF
00H – 80H
CLKSRC0
CLKSRC1
for LCLK1
for LCLK4
CapLoad
XDRV(1)
PB(5)
CLK6
Q(5)
D5
25 – 50 MHz
(5)
D4
1
0
1
60Ω
01
10
10
10
bits in the register are reserved and should be programmed as
shown in Table 3.
Using an External Clock as the Reference Input
The CY22150 can also accept an external clock as reference,
with speeds up to 133 MHz. With an external clock, the XDRV
(register 12H) bits must be set according to Table 4.
01
CLKSRC2
CLKSRC0
for LCLK2
for LCLK4
CapLoad
XDRV(1)
Pump(2)
CLK5
PB(4)
Q(4)
XDRV(0)
D4
(4)
1
D3
30Ω
01
01
10
10
12pF to 18pF
CLKSRC1
CLKSRC2
for LCLK2
80H – C0H
XDRV(0)
CapLoad
for CLK5
Pump(1)
LCLK4
PB(3)
Q(3)
D3
(3)
50 – 90 MHz
1
10
D2
0
60Ω
10
10
10
11
CLKSRC0
CLKSRC1
for LCLK2
CapLoad
for CLK5
Pump(0)
LCLK3
PB(2)
Q(2)
D2
(2)
0
1
CLKSRC2
CLKSRC0
for LCLK3
D1
30Ω
CapLoad
for CLK5
0
01
10
10
11
LCLK2
PB(9)
PB(1)
18pF to 30pF
Q(1)
90 – 133 MHz
C0H – FFH
D1
(1)
0
1
CY22150
11
Page 4 of 13
CLKSRC1
CLKSRC2
for LCLK3
CapLoad
for CLK6
LCLK1
PB(0)
PB(8)
60Ω
N/A
D0
Q(0)
10
10
11
0
D0
(0)
0
1