CY22395 Cypress Semiconductor, CY22395 Datasheet
CY22395
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CY22395 Summary of contents
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... CyClocksRT™ support Advanced Features • Serial-programmable • Configurable output buffer • Digital VCXO • High-frequency LVPECL output (CY22394 only) • 3.3/2.5V outputs (CY22395 only) Cypress Semiconductor Corporation Document #: 38-07186 Rev. *B Three-PLL Serial-Programmable Flash-Programmable Clock Generator Benefits • Generates up to three unique frequencies six outputs from an external source. • ...
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... OUTPUT 8-Bit Q PLL2 Divider 4x4 Crosspoint 11-Bit P Switch 8-Bit Q Divider PLL3 11-Bit P 8-Bit Q Divider CY22393 CY22394 CY22395 Specifics Commercial Temperature Industrial Temperature Commercial Temperature Industrial Temperature Commercial Temperature Industrial Temperature XBUF CLKE CLKD 7-Bit CLKC 7-Bit CLKB 7-Bit Divider ...
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... Logic Block Diagram — CY22395 XTALIN OSC. XTALOUT CONFIGURATION FLASH SHUTDOWN/OE SCLK SDAT S2/SUSPEND LCLKA, LCLKB, LCLKD, LCLKE referenced to LVDD Pin Configurations CY22393 16-pin TSSOP CLKC 1 SHUTDOWN/ S2/SUSPEND AGND XTALIN SCLK (S1) 12 XTALOUT 5 SDAT (S0) XBUF 11 GND ...
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... SUSPEND SHUTDOWN Operation The CY22393, CY22394, and CY22395 are a family of parts designed as upgrades to the existing CY22392 device. These parts have similar performance to the CY22392, but provide advanced features to meet the needs of more demanding applications. The clock family has three PLLs which, when combined with the reference, allow up to four independent frequencies to be output six pins ...
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... The serial interface is active even with the SHUTDOWN/OE pin LOW as the serial interface logic uses static components and is completely self-timed. The part will not meet the I current limit with transitioning inputs. CY22393 CY22394 CY22395 is JA DDS Page ...
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... PLL3 180° Phase Xbuf_OE This bit enables the XBUF output when HIGH. For the CY22395, Xbuf_OE = 0. PdnEn This bit selects the function of the SHUTDOWN/OE pin. When this bit is HIGH, the pin is an active LOW shutdown control. When this bit is LOW, this pin is an active HIGH output enable control ...
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... PLL2_Q[7:0] PLL2_P[7:0] PLL2_LF[2:0] PLL3_Q[7:0] PLL3_P[7:0] PLL3_LF[2:0] Osc_Cap[5: PLL1_Q[7:0] PLL1_P[7:0] PLL1_LF[2:0] PLL1_Q[7:0] PLL1_P[7:0] PLL1_LF[2:0] PLL1_Q[7:0] PLL1_P[7:0] PLL1_LF[2:0] PLL1_Q[7:0] PLL1_P[7:0] PLL1_LF[2:0] CY22393 CY22394 CY22395 00H–20H 20H–30H 30H–40H 60Ω 30Ω 60Ω 30Ω ...
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... Acknowledge Pulse During Write Mode the CY22393,CY22394 and CY22395 will respond with an Acknowledge pulse after every eight bits. This is accomplished by pulling the SDAT line LOW during the N*9 clock cycle as illustrated in Figure the number of bytes transmitted) ...
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... When the CY22393,CY22394 and CY22395 receives the slave address with the R/W bit set to a ‘1’, the CY22393,CY22394 and CY22395 issues an acknowledge and transmits the 8-bit word. The master device ...
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... Data Valid to next Bit CLK HIGH VIH CLK VIL LOW Transition to next Bit STOP Figure 4. Start and Stop Frame CY22393 CY22394 CY22395 1 Bit 1 Bit 1 Bit Slave Slave Slave ACK ACK ACK 8-bit Register Data (00H) Stop Signal 1 Bit 1 Bit 1 Bit ...
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... Rise time of SCLK and SDAT Fall time of SCLK and SDAT Stop mode time from SCLK HIGH to SDAT HIGH Stop mode to Start mode Document #: 38-07186 Rev ACK RA7 RA6 RA1 RA0 ACK + Description CY22393 CY22394 CY22395 + ACK + Min. Max. Unit 400 kHz µs 0.6 µ ...
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... – Three-state outputs 3.3V Power Supply; 2 outputs @ 20 MHz; 4 outputs @ 40 MHz 3.3V Power Supply; 2 outputs @ 166 MHz; 4 outputs @ 83 MHz Shutdown active [5] (CY22395 only) Conditions – /2. DD may be powered at any value between 3.465 and 2.375. ...
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... Crossing point referenced to Vdd/2, balanced resistor network (CY22394 only) Peak-to-peak period jitter, P+/P– outputs measured at crossing point (CY22394 only) PLL Lock Time from Power-up [5] (CY22395 only) Conditions Clock output limit, LVCMOS Duty cycle for outputs, defined measured ...
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... Document #: 38-07186 Rev NEW SELECT STABLE new CLK out C LOAD GND Package Type CY22393 CY22394 CY22395 P+/P- out Product Flow Commercial 70°C Commercial 70°C Industrial, –40 to 85°C Industrial, –40 to 85°C Commercial 70°C Page ...
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... TSSOP - Tape and Reel CY22395ZXC-XXX 16-Pin TSSOP CY22395ZXC-XXXT 16-Pin TSSOP - Tape and Reel CY22395ZXI-XXX 16-Pin TSSOP CY22395ZXI-XXXT 16-Pin TSSOP - Tape and Reel CY22395FXC 16-Pin TSSOP CY22395FXCT 16-Pin TSSOP - Tape and Reel CY22395FXI 16-Pin TSSOP CY22395FXIT 16-Pin TSSOP - Tape and Reel Document #: 38-07186 Rev. *B © ...
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... DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-153 6.25[0.246] PACKAGE WEIGHT 0.05 gms 6.50[0.256] Z16.173 ZZ16.173 LEAD FREE PKG. 0.25[0.010] 1.10[0.043] MAX. BSC GAUGE 0°-8° PLANE 0.076[0.003] SEATING PLANE CY22393 CY22394 CY22395 MAX. PART # STANDARD PKG. 0.50[0.020] 0.09[[0.003] 0.70[0.027] 0.20[0.008] 51-85091-*A Page ...
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... CY22394FXI 16-Pin TSSOP CY22394FXIT 16-Pin TSSOP - Tape and Reel CY22395ZXC-XXX 16-Pin TSSOP CY22395ZXI-XXX 16-Pin TSSOP CY22395FXC 16-Pin TSSOP CY22395FX I 16-Pin TSSOP Document #: 38-07186 Rev. *B Package Type CY22393 CY22394 CY22395 Product Flow Commercial 70°C Commercial 70°C Industrial, –40 to 85°C Industrial, – ...
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... CyClocksRT is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07186 Rev. *B CY22393 CY22394 CY22395 Page ...
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... Document History Page Document Title: CY22393/CY22394/CY22395 Three-PLL Serial-Programmable Flash-Programmable Clock Generator Document Number: 38-07186 Issue REV. ECN NO. Date ** 111984 12/09/01 *A 129388 10/13/03 *B 237755 See ECN Document #: 38-07186 Rev. *B Orig. of Change Description of Change DSG Change from Spec number: 38-01144 to 38-07186 RGL Added timing information ...