CY22395 Cypress Semiconductor, CY22395 Datasheet - Page 7

• Manufacturer Part Number: CY22395
• Description: (CY22393 / CY22394 / CY22395) Three-PLL Serial-Programmable Flash-Programmable Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07186 Rev. *B
OscCap[5:0]
This controls the internal capacitive load of the oscillator. The
approximate effective crystal load capacitance is:
Set to zero for external reference clock.
OscDrv[1:0]
These bits control the crystal oscillator gain setting. These
should always be set according to the following table. The
parameters are the Crystal Frequency, Internal Crystal
Parasitic Resistance (available from the manufacturer), and
the OscCap setting during crystal start-up (which occurs when
power is applied, or after shutdown is released). If in doubt,
use the next higher setting.
Serial Programming Bitmaps — Summary Tables
Addr
Addr
0CH
0DH
08H
09H
0AH
0BH
0EH
0FH
10H
12H
13H
14H
15H
16H
17H
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
11H
DivSel
(1,0)
000
001
010
011
C
S2
0
1
0
1
–
–
–
–
–
–
–
–
–
–
–
–
LOAD
ClkA_FS[0]
ClkA_FS[0]
ClkB_FS[0]
ClkB_FS[0]
ClkC_FS[0]
ClkD_FS[0]
=
Reserved
Reserved
Clk{C,X}_ACAdj[1:0]
DivSel
DivSel
DivSel
DivSel
6pF
b7
b7
ClkX_DCAdj[1]
ClkD_FS[2:1]
+
(
OscCap
PLL2_En
PLL3_En
PLL1_En
PLL1_En
PLL1_En
PLL1_En
b6
b6
×
0.375pF
Clk{A,B,D,E}_ACAdj[1:0]
)
Clk{D,E}_DCAdj[1]
b5
b5
Osc_Cap[5:0]
ClkC_FS[2:1]
PLL2_LF[2:0]
PLL3_LF[2:0]
PLL1_LF[2:0]
PLL1_LF[2:0]
PLL1_LF[2:0]
PLL1_LF[2:0]
b4
b4
PLL2_Q[7:0]
PLL3_Q[7:0]
PLL1_Q[7:0]
PLL1_Q[7:0]
PLL1_Q[7:0]
PLL1_Q[7:0]
For external reference, the following table must be used.
Reserved
These bits must be programmed LOW for proper operation of
the device.
PLL2_P[7:0]
PLL3_P[7:0]
PLL1_P[7:0]
PLL1_P[7:0]
PLL1_P[7:0]
PLL1_P[7:0]
Crystal Freq\ R 30Ω
External Freq (MHz)
15–20 MHz
20–25 MHz
25–30 MHz
8–15 MHz
OscCap
OscDrv[1:0]
ClkC_Div[6:0]
ClkD_Div[6:0]
ClkA_Div[6:0]
ClkA_Div[6:0]
ClkB_Div[6:0]
ClkB_Div[6:0]
PdnEn
b3
b3
ClkC_DCAdj[1]
ClkB_FS[2:1]
00
01
01
10
00H–20H
PLL2_PO
PLL3_PO
PLL1_PO
PLL1_PO
PLL1_PO
PLL1_PO
Xbuf_OE
1–25
b2
b2
60Ω
00
01
10
10
10
25–50
30Ω
01
01
10
10
20H–30H
01
Clk{A,B}_DCAdj[1]
b1
b1
60Ω
ClkE_Div[1:0]
ClkA_FS[2:1]
Osc_Drv[1:0]
PLL2_P[9:8]
PLL3_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
10
10
10
11
50–90
10
CY22393
CY22394
CY22395
Page 7 of 19
30Ω
01
10
10
11
30H–40H
90–166
b0
b0
11
60Ω
NA
10
10
11