CY23FS08 Cypress Semiconductor, CY23FS08 Datasheet

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CY23FS08

Manufacturer Part Number
CY23FS08
Description
Failsafe 2.5 V/3.3 V Zero Delay Buffer
Manufacturer
Cypress Semiconductor
Datasheet

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Features
Cypress Semiconductor Corporation
Document Number: 38-07518 Rev. *F
Logic Block Diagram
Internal DCXO for continuous glitch-free operation
Zero input-output propagation delay
100 ps typical output cycle-to-cycle jitter
110 ps typical output-output skew
1 MHz to 200 MHz reference input
Supports industry standard input crystals
200 MHz (commercial), 166 MHz (industrial) outputs
5 V-tolerant inputs
Phase-locked loop (PLL) bypass mode
Dual reference inputs
28-pin SSOP
Split 2.5 V or 3.3 V output power supplies
3.3 V core power supply
Industrial temperature available
REFSEL
REF1
REF2
FBK
S[4:1]
4
XIN XOUT
Failsafe
Decoder
DCXO
Block
198 Champion Court
TM
Failsafe™ 2.5 V/3.3 V Zero Delay Buffer
PLL
Functional Description
The CY23FS08 is a FailSafe™ Zero Delay Buffer with two
reference clock inputs and eight phase-aligned outputs. The
device provides an optimum solution for applications where
continuous operation is required in the event of a primary clock
failure.
Continuous, glitch-free operation is achieved by using a DCXO,
which serves as a redundant clock source in the event of a
reference clock failure by maintaining the last frequency and
phase information of the reference clock.
The unique feature of the CY23FS08 is that the DCXO is in fact
the
(phase-aligned) to the external reference clock. When this
external
resynchronizes to the external clock.
The frequency of the crystal connected to the DCXO, must be
chosen to be an integer factor of the frequency of the reference
clock. This factor is set by four select lines: S[4:1]. see
The CY23FS08 has three split power supplies; one for core,
another for Bank A outputs, and the third for Bank B outputs.
Each output power supply, except VDDC can be connected to
either 2.5 V or 3.3 V. VDDC is the power supply pin for internal
circuits and must be connected to 3.3 V.
primary
clock
San Jose
clocking
is
,
4
4
CA 95134-1709
restored,
FAIL# /SAFE
source,
CLKA[1:4]
CLKB[1:4]
the
which
Revised January 7, 2011
DCXO
CY23FS08
is
408-943-2600
synchronized
automatically
Table
2.
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CY23FS08 Summary of contents

Page 1

... The unique feature of the CY23FS08 is that the DCXO is in fact the primary (phase-aligned) to the external reference clock. When this external resynchronizes to the external clock ...

Page 2

... Absolute Maximum Conditions..................................... 10 Recommended Pullable Crystal Specifications ........... 10 Operating Conditions..................................................... 10 www.DataSheet4U.com Document Number: 38-07518 Rev Electrical Characteristics ........................................ 11 Switching Characteristics.............................................. 11 Ordering Information....................................................... 11 Package Diagram............................................................ 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 CY23FS08 Page [+] Feedback ...

Page 3

... Reference select. Selects the active reference clock from either REF1 or REF2. When REFSEL = 1, REF1 is selected. When REFSEL = 0, REF2 is selected. REF(MHz) OUT(MHz) Min Max Min PLL and DCXO Bypass mode 16.67 60.00 8.33 30.00 57.00 180.00 28.50 90.00 CY23FS08 Description [3] REF:OUT REF:XTAL Out:XTAL Ratio Ratio Ratio Max 2 2  Page ...

Page 4

... The technique implemented in this design completely eliminates any switching of references to the PLL, greatly simplifying system design. The CY23FS08 PLL is driven by the crystal oscillator, which is phase-aligned to an external reference clock so that the output of the device is effectively phase-aligned to reference via the external feedback loop ...

Page 5

... Output Fail#/Safe www.DataSheet4U.com Document Number: 38-07518 Rev. *F Figure 3. Fail#/Safe Timing Formula Conditions Measured at 80% to 20%, Load = 15 pF Measured at 80% to 20%, Load = FSL CY23FS08 Min Max See Figure 3 See Figure 3 Reference + 300 ppm Reference - 300 ppm Output + 300 ppm ...

Page 6

... Because of the DCXO architecture, the CY23FS08 has a much lower bandwidth than a typical PLL-based clock generator. This is shown in Figure 6. This low bandwidth makes the CY23FS08 also useful as a jitter attenuator. The loop bandwidth curve is also known as the jitter transfer curve. www.DataSheet4U.com Document Number: 38-07518 Rev. *F Figure 5 ...

Page 7

... Figure 8. Input Slew Rate 70% 70% 30% 30 SR(I) SR(I) Figure 9. Output Slew Rate 80% 80% 20 SR(O) SR(O) Figure 10. Output to Output Skew and Intrabank Skew Figure 11. Part to Part Skew SK(PP) CY23FS08 Page [+] Feedback ...

Page 8

... C LOADMIN LOADMIN )) – ( ))] * 10 LOADMIN LOADMAX CY23FS08 (for minimum value), and C LOADMIN LOADMAX range “center” is approximately 20 pF, but LOAD Figure 13. In this example, specifying a XTAL )) – ( ))] ...

Page 9

... Positive Capture Range = 333 ppm – 53 ppm = +280 ppm It is important to note that the XTAL with lower C0/C1 ratio has wider pullability/capture range as compared to the higher C0/C1 ratio. This helps to select the appropriate XTAL for use in the FailSafe application. CY23FS08 ) C0/C1 = 200 C0/C1 = 300 C0/C1 = 400 ...

Page 10

... Comments Parallel resonance, fundamental mode, AT cut Fundamental mode Ratio used because typical R values 1 are much less than the maximum spec No external series resistor assumed High side NOM Low side NOM Description CY23FS08 Min Max Unit –0.5 4.6 V –0 0.5 VDC DD –65 150 °C – ...

Page 11

... DD 6.25 MHz Load = 15 pF, f OUT At room temperature with 18.432 MHz Crystal Package Type 28-pin SSOP 28-pin SSOP – Tape and Reel 28-pin SSOP 28-pin SSOP – Tape and Reel CY23FS08 Min Typ Max Unit – – 0.3×V DD 0.7×V – ...

Page 12

... Ordering Code Definition (T) CY23FS08 OX X Package Diagram Figure 14. 28-pin (5.3 mm) Shrunk Small Outline Package SP28 www.DataSheet4U.com Document Number: 38-07518 Rev. *F Package type tape and reel, blank = tube Temperature code Commercial Industrial Package: 28-pin SSOP, Pb-free Device number CY23FS08 51-85079 *D Page [+] Feedback ...

Page 13

... Document Number: 38-07518 Rev. *F Document Conventions Units of Measure Symbol Unit of Measure  C degree Celsius µA micro Amperes mA milli Amperes ms milli seconds MHz Mega Hertz ns nano seconds pF pico Farad ps pico seconds ppm parts per million W Watts  ohms V Volts CY23FS08 Page [+] Feedback ...

Page 14

... Document History Page Document Title: CY23FS08 Failsafe™ 2.5 V/3.3 V Zero Delay Buffer Document Number: 38-07518 Submission Rev. ECN No. Date ** 123699 04/23/03 *A 224067 See ECN *B 276749 See ECN *C 417645 See ECN *D 2865396 01/25/2010 *E 2925613 04/30/10 *F 3130032 01/06/2011 www.DataSheet4U.com Document Number: 38-07518 Rev. *F Orig. of Description of Change ...

Page 15

... FailSafe is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. cypress.com/go/clocks cypress.com/go/plc cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB Revised January 7, 2011 CY23FS08 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 ...

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