CY23FS08 Cypress Semiconductor, CY23FS08 Datasheet - Page 3

• Manufacturer Part Number: CY23FS08
• Description: Failsafe 2.5 V/3.3 V Zero Delay Buffer
• Manufacturer: Cypress Semiconductor

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Pinouts
Table 1. Pin Definitions
Table 2. Configuration Table
Document Number: 38-07518 Rev. *F
Notes
1. For normal operation, connect either one of the eight clock outputs to the FBK input.
2. Weak pull downs on all CLK outputs.
3. Weak pull ups on these inputs.
4. Weak pull downs on these inputs.
S[4:1]
0000
1000
1110
Pin Number
25,24,19,18
4,5,10,11
23,6,7,22
17,21
20,26
8,12
1,2
3,9
27
14
15
16
13
28
8.33
9.50
Min
XTAL (MHz)
REF1,REF2
CLKB[1:4]
CLKA[1:4]
FBK
S[1:4]
XIN
XOUT
FAIL#/SAFE
VDDC
VDDB
VSSB
VDDA
VSSA
REFSEL
Pin Name
Max
30
30
Reference clock inputs.
Bank B clock outputs.
Bank A clock outputs.
Feedback input to the PLL.
Frequency select pins/PLL and DCXO bypass.
Reference crystal input.
Reference crystal output.
Valid reference indicator. A high level indicates a valid reference input.
3.3 V power supply for the internal circuitry.
2.5 V or 3.3 V power supply for Bank B outputs.
Ground.
2.5 V or 3.3 V power supply for Bank A outputs.
Ground.
Reference select. Selects the active reference clock from either REF1 or REF2.
When REFSEL = 1, REF1 is selected. When REFSEL = 0, REF2 is selected.
16.67
57.00
Min
REF(MHz)
CLKB1
CLKB2
CLKB3
CLKB4
VDDB
VDDC
VDDB
VSSB
VSSB
REF1
REF2
Figure 1. Pin Configuration
XIN
180.00
S3
60.00
S2
Max
10
11
12
13
14
9
1
2
3
4
5
6
7
8
28-pin SSOP
[1, 2]
[1, 2]
[4]
5 V tolerant.
28.50
8.33
[1]
Min
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PLL and DCXO Bypass mode
OUT(MHz)
CLKA2
S1
FAIL#/SAFE
XOUT
REFSEL
FBK
VSSA
CLKA1
S4
VDDA
VSSA
CLKA3
CLKA4
VDDA
30.00
90.00
Description
Max
[3]
REF:OUT
Ratio
2
2
REF:XTAL
Ratio
2
6
CY23FS08
Out:XTAL Ratio
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