CY25822-2 Cypress Semiconductor, CY25822-2 Datasheet - Page 4

• Manufacturer Part Number: CY25822-2
• Description: CK-SSC Spread Spectrum Clock Generator
• Manufacturer: Cypress Semiconductor

Table 4. Spread Spectrum Select (continued)
Byte 1: Control Register
Bytes 2 through 5: Reserved Registers
Byte 6: Vendor/Revision ID Register
Document #: 38-07531 Rev. **
Bit
7
6
5
4
3
2
1
0
SS3
Bit
7
6
5
4
3
2
1
0
0
0
0
1
1
1
1
1
1
1
1
@Pup
0
0
0
0
1
0
0
0
@Pup
SS2
1
1
0
0
1
1
0
0
Pin#
1
1
1
0
0
0
0
1
1
1
1
–
–
–
–
–
–
–
–
Name
Pin#
SS1
–
–
–
–
–
–
–
–
0
1
1
0
0
1
1
0
0
1
1
5
5
4
4
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
REFEN
REFSLEW
Not Applicable
Not Applicable
CLKSLEW
CLKEN
Not Applicable
Not Applicable
Pin Description
SS0
1
0
1
0
1
0
1
0
1
0
1
Name
Spread Mode
PWRDWN# (Power-down) Clarification
The PWRDWN# (Power-down) pin is used to shut off ALL
clocks prior to shutting off power to the device. PWRDWN# is
an asynchronous active LOW input. This signal is synchro-
nized internally to the device powering down the clock synthe-
sizer. PWRDWN# is an asynchronous function for powering up
the system. When PWRDWN# is low, all clocks are driven to
a LOW value and held there and the VCO and PLLs are also
powered down. All clocks are shut down in a synchronous
manner so has not to cause glitches while transitioning to the
low ‘stopped’ state. When PWRDWN# is deasserted the
clocks should remain stopped until the VCO is stable and
within specification (t
tri-stated or driven low depending on the state of the tri-state
enable I
driven state are driven low.
The CLKIN input must be on and within specified operating
parameters before PWRDWN# is asserted and it must remain
in this state while PWRDWN# is asserted.
Center
Center
Center
Center
Center
Center
Center
Center
Down
Down
Down
REFOUT enable
0 = disabled, 1 = enabled
REFOUT edge rate control
0 = slow, 1 = nominal
Reserved.
Reserved
CLKOUT edge rate control
0 = slow, 1 = nominal
CLKOUT enable
0 =disabled, 1 = enabled
Reserved
Reserved
2
C register bit. CY25822 clocks that are stopped in the
STABLE
Pin Description
). A stopped clock is either
Spread Amount%
www.DataSheet4U.com
±1.25
±0.3
±0.4
±0.5
±0.6
±0.8
±1.0
±1.5
2.0
2.5
3.0
CY25822-2
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