CY28301 Cypress Semiconductor, CY28301 Datasheet
CY28301
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CY28301 Summary of contents
Page 1
... SDRAM11 SDRAM10 VDD_48MHz GND_SDRAM 48MHz/FS0 Note: 24_48MHz 1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH. • 3901 North First Street • CY28301 ® Integrated Chipset [ REF/FS1 VDD_APIC ...
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... Power Connection: Power supply for SDRAM output buffers, PCI output buffers, reference output buffers, and 48-MHz output buffers. Connect to 3.3V. P 2.5V Power Connection: Power supply for APIC and CPU output buffers. Connect to 2.5V. G Ground Connections: Connect all ground pins to the common system ground plane. CY28301 Page ...
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... Serial Data Interface The CY28301 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol supports byte/word Write, byte/word Read, block Write, and block Read operations from Table 1 ...
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... Acknowledge from slave 20 Repeat start 21:27 Slave address – 7 bits 28 Read 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Not Acknowledge 39 Stop CY28301 Page ...
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... CY28301 Serial Configuration Map 1. The serial bits will be read by the clock driver in the following order: Byte 0 – Bits Byte 0: Control Register 0 Bit Pin# Bit 7 – Bit 6 – Bit 5 – Bit 4 – Bit 3 – Bit 2 – Bit 1 – ...
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... SDRAM7 1 (Active/Inactive) SDRAM6 1 (Active/Inactive) SDRAM5 1 (Active/Inactive) SDRAM4 1 (Active/Inactive) SDRAM3 1 (Active/Inactive) SDRAM2 1 (Active/Inactive) SDRAM1 1 (Active/Inactive) SDRAM0 1 (Active/Inactive) Name Default Reserved 0 Reserved Reserved 0 Reserved Reserved 0 Reserved SDRAM_F 1 (Active/Inactive) SDRAM11 1 (Active/Inactive) SDRAM10 1 (Active/Inactive) SDRAM9 1 (Active/Inactive) SDRAM8 1 (Active/Inactive) CY28301 Description Description Description Description Page ...
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... SDRAM clock output drive strength 0 = Normal 1 = High Drive 0 PCI and AGP clock output drive strength 0 = Normal 1 = High drive 0 Reserved 0 Reserved 0 Reserved 0 Reserved Pin Description Pin Description Reserved 0 = Norm High drive 0 = Norm High drive Reserved (Active/Inactive) (Active/Inactive) Reserved Reserved Pin Description Pin Description CY28301 Page ...
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... AGP skew control 00 = Normal –150 +150 +300 ps Default 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved Default 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved 0 Reserved CY28301 Pin Description Description Pin Description Pin Description Page ...
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... Reserved. Write with ‘1’ Reserved 1 Reserved. Write with ‘1’ Name Default Reserved 0 Reserved Reserved 0 Reserved Reserved 0 Reserved Reserved 0 Reserved Reserved 0 Reserved Reserved 0 Reserved Reserved 0 Reserved Name Default Reserved 0 Reserved Reserved 0 Reserved CY28301 Pin Description Description Description Description Description Page ...
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... CPU SDRAM 66.6 100.0 100.0 100.0 133.3 133.3 133.3 100.0 [2] Description Description Condition 3.3V ±5% 3.3V ±5% 2.5V ±5% V DD3 [3] 0 < V <V in DD3 I = (–1 mA mA) ol CY28301 Description 3V66 PCI APIC 66.6 33.3 66.6 33.3 66.6 33.3 66.6 33.3 Min. Max. –0.5 4.6 –0.5 3.6 –65 150 Min. Max. –0.5 4.6 –0.5 3.6 2000 Min. Max. ...
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... Xtal Pin Capacitance xtal C Output Pin Capacitance out L Pin Inductance pin T Ambient Temperature a Document #: 38-07011 Rev. *C Condition Min (– (–1 mA) 2 mA airflow 0 CY28301 Max. Unit °C Page ...
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... V A DDQ3 66.6-MHz Host 100-MHz Host Min. Max. Min. 15.0 15.5 10.0 5.2 N/A 3.0 5.0 N/A 2.8 0.4 1.6 0.4 0.4 1.6 0.4 10.0 10.5 10.0 3.0 N/A 3.0 2.8 N/A 2.8 0.4 1.6 0.4 0.4 1.6 0.4 60.0 64.0 60.0 25.5 N/A 25.5 25.3 N/A 25.30 0.4 1.6 0.4 0.4 1.6 0.4 15.0 16.0 15.0 5.25 N/A 5.25 5.05 N/A 5.05 0.5 2.0 0.5 0.5 2.0 0.5 30.0 N/A 30.0 12.0 N/A 12.0 12.0 N/A 12.0 0.5 2.0 0.5 0.5 2.0 0.5 1.0 10.0 1.0 1.0 10.0 1.0 3 achieves its nominal operating level (typical condition V DDQ3 = 0.4V and V ol CY28301 = 2.5V ± 14.31818 MHz) DDQ2 XTL 133-MHz Host Max. Min. Max. Unit 10.5 7.5 8.0 ns N/A 1.87 N/A ns N/A 1.67 N/A ns 1.6 0.4 1.6 ns 1.6 0.4 1.6 ns 10.5 10.0 10.5 ns N/A 3.0 N/A ns N/A 2.8 N/A ns 1.6 0.4 1.6 ns 1.6 0.4 1.6 ns N/A 60.0 64.0 ns N/A 25.5 N/A ns N/A 25.30 N/A ns 1.6 0.4 1.6 ns 1.6 0.4 1.6 ns 16.0 15.0 16.0 ns N/A 5.25 N/A ns N/A 5.05 N/A ns 2.0 0.5 2.0 ns 2.0 0.5 2.0 ns N/A 30.0 N/A ns N/A 12 ...
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... Output Test Point Buffer Test Load T PERIOD Duty Cycle T HIGH T LOW T T RISE FALL T HIGH 2.4 1.5 0 RISE FALL Figure 1. Output Buffer CY28301 Skew, Jitter Nom. V Measure Point DD 2.5V 1.25V 3.3V 1.5V 2.5V 1.25V 3.3V 1.5V 3.3V 1.5V 3.3V 1.5V 3.3V 1.5V T PERIOD Duty Cycle T LOW Page ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Type 56-Lead Shrunk Small Outline Package O56 CY28301 Operating Range Commercial, 0°C to 70°C Commercial, 0°C to 70°C ...
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... Document History Page Document Title: CY28301 Frequency Generator for Intel Document Number: 38-07011 ECN Issue REV. NO. Date ** 106533 06/27/01 *A 109365 11/06/01 *B 118785 09/25/02 *C 122717 12/21/02 Document #: 38-07011 Rev. *C ® Integrated Chipset Orig. of Change Description of Change IKA Change from Spec #: 38-01096 to 38-07011 Changed I2C to SMBus and Updated Byte Tables ...