CY28301 Cypress Semiconductor, CY28301 Datasheet - Page 2

• Manufacturer Part Number: CY28301
• Description: Frequency Generator for Intel Integrated Chipset
• Manufacturer: Cypress Semiconductor

Pin Definitions
Document #: 38-07011 Rev. *C
REF/FS1
X1
X2
PCI0
PCI1
PCI2/SEL24_48MHz#
PCI3:7
3V66_0:2
48MHz/FS0
24_48MHz
PD#
CPU0:1
SDRAM0:11,
SDRAM_F
APIC
SDATA
SCLK
VDD_REF,
VDD_3V66, VDD_PCI,
VDD_SDRAM,
VDD_48MHz
VDD_CPU,
VDD_APIC
GND_REF,
GND_3V66,
GND_PCI,
GND_SDRAM,
GND_48MHZ,
GND_CPU
Pin Name
1, 9, 10, 18, 25,
4, 5, 14, 21, 28,
15, 16, 17, 19,
48, 47, 46, 44,
43, 42, 40, 39,
31, 30, 27, 26,
29, 41, 49, 50,
32, 37, 45, 33
Pin No.
6, 7, 8
52, 51
53, 55
56
12
13
20
34
35
22
38
54
24
23
36
11
2
3
Type
Pin
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
G
P
P
I
I
I
Reference Clock /Frequency Select 1: 3.3V 14.318-MHz clock output.
This pin also serves as the select strap to determine the device operating
frequency (as described in Table 5).
Crystal Input: This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency
input.
Crystal Output: An input connection for an external 14.318-MHz crystal
connection. If using an external reference, this pin must be left
unconnected.
PCI Clock 0: 3.3V 33-MHz PCI clock output.
PCI Clock 1: 3.3V 33-MHz PCI clock output.
PCI Clock 2/Select 24 or 48 MHz: 3.3V 33-MHz PCI clock outputs. This
pin also serves as the select strap to determine the output frequency for
24_48MHz output. Logic 1 = 24 MHz on pin 35.
PCI Clock 3 through 7: 3.3V 33-MHz PCI clock outputs. PCI0:7 can be
individually turned off via the SMBus interface.
66-MHz Clock Output: 3.3V output clocks. The operating frequency is
controlled by FS0:1 (see Table 5).
48-MHz Output/Frequency Selection 1: 3.3V 48-MHz non-spread
spectrum output. This pin also serves as the select strap to determine the
device operating frequency (as described in Table 5.)
24- or 48-MHz Output: 3.3V 24- or 48-MHz non-spread spectrum output.
Power-down Input: LVTTL-compatible asynchronous input that places
the device in power-down mode when held LOW.
CPU Clock Outputs: Clock outputs for the host bus interface. Output
frequencies depending on the configuration of FS0:1. Voltage swing is set
by VDDQ2.
SDRAM Clock Outputs: 3.3V outputs for SDRAM and chipset. The
operating frequency is controlled by FS0:1 (see Table 5).
Synchronous APIC Clock Outputs: Clock outputs running synchronous
with the PCI clock outputs. Voltage swing set by VDDQ2.
Data pin for SMBus circuitry.
Clock pin for SMBus circuitry.
3.3V Power Connection: Power supply for SDRAM output buffers, PCI
output buffers, reference output buffers, and 48-MHz output buffers.
Connect to 3.3V.
2.5V Power Connection: Power supply for APIC and CPU output buffers.
Connect to 2.5V.
Ground Connections: Connect all ground pins to the common system
ground plane.
Pin Description
CY28301
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