CY28400 Cypress Semiconductor, CY28400 Datasheet
CY28400
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CY28400 Summary of contents
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... HIGH_BW# PLL Cypress Semiconductor Corporation Document #: 38-07591 Rev. ** Functional Description The CY28400 is a differential buffer and serves as a companion device to the CK409 or CK410 clock generator. The device is capable of distributing the Serial Reference Clock (SRC) in PCI Express and SATA implementations. DIFT1 DIFC1 ...
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... The slave receiver address is 11011100 (DCh). Description Block Read Protocol Bit 1 Start 2:8 Slave address – 7 bits 9 Write = 0 10 Acknowledge from slave 11:18 Command Code – 8 bits '00000000' stands for block operation 19 Acknowledge from slave 20 Repeat start CY28400 Description Description Page ...
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... Acknowledge from slave 20 Repeat start 21:27 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Acknowledge from master 39 Stop Description CY28400 Page ...
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... Free-running Stopped with SRC_STOP# Reserved Reserved Allow Control DIFT/C2 with assertion of SRC_STOP Free-running Stopped with SRC_STOP# Allow Control DIFT/C1 with assertion of SRC_STOP Free-running Stopped with SRC_STOP# Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CY28400 Description Description Description Description Page ...
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... DIFT pin driven high Iref and DIFC three-state. However, if the control register PWRDWN# drive mode bit is programmed to ‘1’, then both DIFT and the DIFC are three-stated. Figure 1. PWRDWN# Assertion Diagram CY28400 Description Description Page ...
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... PWRDWN# deasserted with the PLL locked and stable are the DIF outputs enabled. Document #: 38-07591 Rev. ** Tstable <1mS Tdrive_Pwrdwn# <300uS, >200mV Figure 2. PWRDWN# Deassertion Diagram Description No Input Clock S1 Wait for Input Clock & Delay PWRDWN# De- assertion PWRDWN# Asserted S0 Normal Operation Figure 3. Buffer Power-up State Diagram S2 S3 CY28400 Page ...
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... DIFT/C outputs resuming simultaneously. If the control register three-state bit is programmed to ‘1’ (three-state), then all stopped DIFT outputs will be driven high within SRC_STOP# deassertion to a voltage greater than 200 mV. CY28400 DIFC Normal Low 1mS ...
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... The impact of writing a ‘0’ to the SRC_DIV/2 register bit is all DIF outputs will transition cleanly in a glitch-free manner from latency from the normal operation (output frequency equal to input) to half the input frequency within 2–6 DIF clock periods. CY28400 1mS 1mS DIFT DIFC Normal Normal ...
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... PLL peaking when two or more buffers are cascaded by staggering device bandwidths. The PLL low bandwidth mode may be selected in two ways, via writing a ‘0’ to SMBus register bit or by asserting the HIGH_BW# pin is low or both, the device will be configured for low bandwidth operation. CY28400 Page ...
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... PD asserted, Outputs driven PD asserted, Outputs Three-stated Condition DIF at 0.7V Measured at crossing point Measured at crossing point V OX Measured at crossing point V OX Measured from V = 0.175 Determined as a fraction of 2*(T R Measured SE Measured SE CY28400 Min. Max. Unit –0.5 4.6 –0.5 4.6 –0 0.5 VDC DD –65 150 0 70 – ...
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... Ω Ω Ω tia lly Figure 8. Differential Clock Termination TRise (CLOCK) TFall (CLOCK) CY28400 Min. 250 – – – 0.2 – OX 2.5 ...
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... Ordering Code CY28400OC CY28400OCT Document #: 38-07591 Rev LOW V UDS T PERIOD High Duty Cycle % Package Type 28-pin SSOP 28-pin SSOP (Tape & Reel) CY28400 ,V and V OVS UDS RB Low Duty Cycle % Operating Range Commercial, 0° °C Commercial, 0° °C Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY28400 51-85079-*C ...
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... Document History Page Document Title: CY28400 100-MHz Differential Buffer for PCI Express and SATA Document Number: 38-07591 Rev. ECN No. Issue Date ** 130190 11/26/03 Document #: 38-07591 Rev. ** Orig. of Change RGL New Data Sheet CY28400 Description of Change Page ...