CY28400 Cypress Semiconductor, CY28400 Datasheet - Page 7

• Manufacturer Part Number: CY28400
• Description: 100-MHz Differential Buffer for PCI Express and SATA
• Manufacturer: Cypress Semiconductor

Document #: 38-07591 Rev. **
SRC_STOP# Clarification
The SRC_STOP# signal is an active low input used for clean
stopping and starting the DIF outputs (valid clock must be
present on SRCT_IN). The SRC_STOP# signal is a
de-bounced signal in that it’s state must remain unchanged
during two consecutive rising edges of DIFC to be recognized
as a valid assertion or deassertion. (The assertion and
deassertion of this signal is absolutely asynchronous).
Table 5. SRC_STOP# Functionality
SRC_STOP# Assertion
The impact of asserting the SRC_STOP# pin is all DIF outputs
that are set in the control registers to stoppable via assertion
of SRC_STOP# are stopped after their next transition. When
the
programmed to ‘0’, the final state of all stopped DIFT/C signals
is DIFT clock = High and DIFC = Low. There is to be no change
to the output drive current values, DIFT will be driven high with
a current value equal 6 x Iref, and DIFC will not be driven.
When the control register SRC_STOP# three-state bit is
programmed to ‘1’, the final state of all stopped DIF signals is
low, both DIFT clock and DIFC clock outputs will not be driven.
Note:
4. In the case where OE is asserted high, the output will always be three-stated regardless of SRC_STOP# drive mode register bit state.
control
DIFC(Free Running
DIFC(Free Running
DIFT(Free Running
DIFT(Free Running
DIFC (Stoppable)
DIFC (Stoppable)
DIFT (Stoppable)
DIFT (Stoppable)
SRC_STOP#
register
SRC_STOP#
SRC_STOP#
PWRDWN#
PWRDWN#
1
0
SRC_STOP#
Figure 5. SRC_STOP# =Driven, PWRDWN# = Three-state
Figure 4. SRC_STOP# = Driven, PWRDWN# = Driven
[4]
three-state
bit
Iref * 6 or Float
is
Normal
DIFT
SRC_STOP# Deassertion
All differential outputs that were stopped will resume normal
operation in a glitch-free manner. The maximum latency from
the deassertion to active outputs is between 2–6 DIFT/C clock
periods (two clocks are shown) with all DIFT/C outputs
resuming simultaneously. If the control register three-state bit
is programmed to ‘1’ (three-state), then all stopped DIFT
outputs will be driven high within 10 ns of SRC_STOP#
deassertion to a voltage greater than 200 mV.
Normal
DIFC
Low
1mS
1mS
CY28400
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