CY28435 Cypress Semiconductor, CY28435 Datasheet
CY28435
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CY28435 Summary of contents
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... SRCT4_SATA SRCC4_SATA 27 30 VDD_SRC indicates internal pull-up ** indicates internal pull-down , • San Jose CA 95134 • Revised December 21, 2004 CY28435 USB x 2 PCI2/DF1 PCI1/DF0 PCI0/SRESET# REF1/**FS_C REF0/**FS_D VSS_REF XIN XOUT VDD_REF SDATA SCLK VSS_CPU CPUT0 CPUC0 VDD_CPU CPUT1 ...
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... SMBus-compatible SCLOCK. I/O SMBus-compatible SDATA. PWR 3.3V power supply for outputs 14.318-MHz crystal output. I 14.318-MHz crystal input. GND Ground for outputs. 3.3V-tolerant input for CPU frequency selection/Reference clock. PD Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. CY28435 Description Page ...
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... Figure 1. CPU and SRC Frequency Select Tables CY28435 Description when VTT_PWRGD# is asserted LOW. IHFS_C ,V ,V ILFS_C IMFS_C IHFS_C CPU M CPU N CPU N SRC PLL SRC M divider DEFAULT allowable Gear divider (not ...
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... Data byte 1 from slave – 8 bits 47 Acknowledge 55:48 Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge .... Stop Byte Read Protocol Bit 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave CY28435 Description Description Page ...
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... CPU[T/C]1 Output Enable 0 = Disable (Tri-state Enabled CPU[T/C]0 Output Enable 0 = Disable (Tri-state Enabled CPU PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off Spread on CY28435 Byte Read Protocol Description Command Code – 8 bits Acknowledge from slave Repeated start Slave address – 7 bits Read Acknowledge from slave Data from slave – ...
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... Free running Stopped with PCI_STP# PCIF1 Allow control of PCIF1 with assertion of SW PCI_STP Free running Stopped with PCI_STP# PCIF0 Allow control of PCIF0 with assertion of SW PCI_STP Free running Stopped with PCI_STP# RESERVED, Set = 1 RESERVED, Set = 1 RESERVED, Set = 1 CY28435 Description Description Description Page ...
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... FS_A Reflects the value of the FS_A pin sampled on power- FS_A was LOW during VTT_PWRGD# assertion Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 CY28435 Description Description Description Page ...
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... WD_Alarm is set to “1” when the watchdog times out reset to “0” when the system clears the WD_TIMER time stamp. Watchdog timer time stamp selection 000: Reserved (test mode) 001 Time_Scale 010 Time_Scale 011 Time_Scale 100 Time_Scale 101 Time_Scale 110 Time_Scale 111 Time_Scale CY28435 Description Description Description Page ...
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... After asserting and deasserting the SRESET# this bit will self clear (set to 0). The SRESET# pin must be enabled by latching SRESET#_EN on VTT_PRWGD# to utilize this feature. FS_Override 0 = Select operating frequency by FS(E:A) input pins 1 = Select operating frequency by FSEL_(4:0) settings CY28435 Description Description Description Description Description Page ...
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... Watchdog Autorecovery Watchdog Autorecovery Mode Crystal Recommendations The CY28435 requires a Parallel Resonance Crystal. Substi- tuting a series resonance crystal will cause the CY28435 to operate at the wrong frequency and violate the ppm specifi- cation. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading ...
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... Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Cs2 Ci .......................................................... Internal capacitance Trace (lead frame, bond wires etc.) 2.8pF Ce2 Trim 33pF CY28435 Motional Tolerance Stability (max.) (max.) (max.) 0.016 pF 35 ppm 30 ppm Load Capacitance (each side – (Cs + Ci) ...
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... The Smooth Switch circuit can be assigned to either PLL via register byte 14 bit 4. By default the smooth switch circuit is assigned to the CPU PLL. Either PLL can still be overclocked when it does not have control of the smooth switch circuit but CY28435 Page ...
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... After the SRESET# pulse is asserted the SW_RESET bit should be automatically cleared by the device. PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous CY28435 Page ...
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... After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Below is an example showing the relationship of clocks coming up. Figure 4. Power-down Assertion Timing Waveform Tstable <1.8ms PD Tdrive_PWRDN# <300µS, >200mV CY28435 Page ...
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... Sample Sels Delay VTT_PW RGD# State 1 State 2 On Figure 6. VTT_PWRGD# Timing Diagram S1 VTT_PWRGD# = Low Delay >0.25mS S3 Normal VDD_A = off Operation VTT_PWRGD# = toggle CY28435 Device is not affected, VTT_PW RGD# is ignored State Sample Inputs straps Wait for <1.8ms Enable Outputs Page ...
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... SDATA, SCLK SDATA, SCLK Except internal pull-up resistors, 0 < V Except internal pull-down resistors, 0 < – max. load and freq. per Figure 10 PD asserted, Outputs Driven PD asserted, Outputs Tri-state CY28435 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD – ...
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... Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX CY28435 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10 – 500 ps – ...
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... Measured from V OL Determined as a fraction of 2*(T T )/( Math averages Figure 10 Math averages Figure 10 See Figure 10. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V CY28435 Min. – OX – = 0.175 175 OH – – – 660 –150 250 – V HIGH – ...
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... Measured between 0.8V and 2.0V Measurement at 1.5V Measurement taken from cross point Vox@1us Measurement taken from cross point Vox@10us Measurement taken from cross point Vox@125us Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V CY28435 Min. 1.0 – – 10.41354 10.41979 OX 10.16354 10.66979 OX – ...
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... Figure 8. Single-ended Load Configuration 12Ω 60Ω 12Ω PCI/ USB 60Ω 12Ω 60Ω 12Ω REF 60Ω 12Ω 60Ω CY28435 Min. Max. 1.0 4.0 – 1000 – 1.8 Measurement Point 5pF Measurement Point 5pF Measurement Point 5pF Measurement Point 5pF ...
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... Package Type Product Flow Commercial, 0° to 85°C Commercial, 0° to 85°C Commercial, 0° to 85°C Commercial, 0° to 85°C CY28435 Page ...
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... GAUGE PLANE MAX. 0.25[0.010] 0.20[0.008] 0.051[0.002] 0.152[0.006] 0.170[0.006] SEATING 0.279[0.011] PLANE 2 C system, provided that the system conforms to the I CY28435 DIMENSIONS IN INCHES MIN. MAX. 0.005 0.010 0.024 0.040 0°-8° 51-85062-*C DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0 ...
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... Document History Page Document Title: CY28435 Clock Generator for Intel Document Number: 38-07664 REV. ECN NO. Issue Date ** 214042 See ECN *A 268575 See ECN *B 305734 See ECN Document #: 38-07664 Rev. *B PRELIMINARY Grantsdale Chipset Orig. of Change RGL New Data Sheet RGL Changed the tri-state test mode from ...