CY28435 Cypress Semiconductor, CY28435 Datasheet - Page 13

• Manufacturer Part Number: CY28435
• Description: Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07664 Rev. *B
it is not guaranteed to transition to the new frequency without
large frequency glitches.
It is not recommended to enable overclocking and change the
N values of both PLLs in the same SMBUS block write.
Watchdog Timer
The Watchdog timer is used in the system in conjunction with
overclocking. It is used to provide a reset to a system that has
hung up due to overclocking the CPU and the Front side bus.
The watchdog is enabled by the user and if the system
completes its checkpoints, the system will clear the timer.
However, when the timer runs out, there will be a reset pulse
generated on the SRESET# pin for 20 ms that is used to reset
the system.
When the Watchdog is enabled (WD_EN = 1) the Watchdog
timer will start counting down from a value of Watchdog_timer
* time scale. If the Watchdog timer reaches 0 before the
WD_EN bit is cleared then it will assert the SRESET# signal
and set the Watchdog Alarm bit to 1.
To use the watchdog the SRESET# pin must be enabled by
SRESET_EN pin being sampled LOW by VTTPWRGD#
assertion during system boot up.
At any point if during the Watchdog timer countdown, if the
time stamp or Watchdog timer bits are changed the timer will
reset and start counting down from the new value.
After the Reset pulse, the watchdog will stay inactive until
either:
Watchdog Register Bits
The following register bits are associated with the Watchdog
timer:
Watchdog Enable – This bit (by default) is not set, which
disables the Watchdog. When set, the Watchdog is enabled.
Also, when there is a transition from LOW to HIGH, the timer
reloads. Default = 0, disable
Watchdog Timer – There will be three bits (for seven combina-
tions) to select the timer value. Default = 000, the value '000'
is a reserved test mode.
Watchdog Alarm – This bit is a flag and when it is set, it
indicates that the timer has expired. This bit is not set by
default. When the bit is set, the user is allowed to clear. Default
= 0.
Watchdog Time Scale – This bit selects the multiplier. When
this bit is not set, the multiplier will be 250 ms. When set (by
default), the multiplier will be 3s. Default = 1
Watchdog Reset Mode – This selects the Watchdog Reset
Mode. When this bit is not set (by default), the Watchdog will
send a reset pulse and reload the recovery frequency depends
on Watchdog Recovery Mode setting. When set, it just send a
reset pulse.Default = 0, Reset & Recover Frequency.
Watchdog Recovery Mode – This bit selects the location to
recover from. One option is to recover from the HW settings
(already stored in SMBUS registers for readback capability)
and the second is to recover from a register called “Recovery
N”. Default = 0 (Recover from the HW setting)
1. A new time stamp or watchdog timer value is loaded.
2. The WD_EN bit is cleared and then set again.
PRELIMINARY
Watchdog Autorecovery Enable – This bit by default is set and
the recovered values are automatically written into the
“Watchdog Recovery Register” and reloaded by the Watchdog
function. When this bit is not set, the user is allowed to write to
the “Watchdog Recovery Register”. The value stored in the
“Watchdog Recovery Register” will be used for recovery.
Default = 1, Autorecovery.
Watchdog Recovery Register – This is a nine-bit register to
store the watchdog N recovery value. This value can be written
by the Auto recovery or User depending on the state of the
“Watchdog Auto Recovery Enable bit”.
Watchdog Recovery Modes
There are three operating modes that require Watchdog
recovery. The modes are Dial-A-Frequency (DAF), Dynamic
Clocking (DF), or Frequency Select. There are 4 different
recovery modes: the following diagram lists the operating
mode and the recovery mode associated with it.
Recover to Hardware M,N, O
When this recovery mode is selected, in the event of a
Watchdog timeout, the original M,N, and O values that were
latched by the HW FSEL pins at chip boot up should be
reloaded.
Autorecovery
When this recovery mode is selected, in the event of a
Watchdog timeout, the M and N values stored in the Recovery
M and N registers should be reloaded. The current values of
M and N will be latched into the internal recovery M and N
registers by the WD_EN bit being set.
Manual Recovery
When this recovery mode is selected, in the event of a
Watchdog timeout, the N value as programmed by the user in
the N recovery register, and the M value that is stored in the
Recovery M register (not accessible by the user) should be
restored. The current M value should be latched M recovery
register by the WD_EN bit being set.
No Recovery
If no recovery mode is selected, in the event of a Watchdog
time out, the device should just assert the SRESET# and keep
the current values of M and N
Software Reset
Software reset is a reset function which is used to send out a
pulse from SRESET# pin. It is controlled by the SW_RESET
enable register bit. Upon completion of the byte/word/block
write in which the SW_RESET bit was set, the device will send
a RESET pulse on the SRESET# pin. The duration of the
SRESET# pulse should be the same as the duration of the
SRESET# pulse after a Watchdog timer time out.
After the SRESET# pulse is asserted the SW_RESET bit
should be automatically cleared by the device.
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual-function pin. During
initial power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled LOW by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
CY28435
Page 13 of 23