CY28437 SpectraLinear, CY28437 Datasheet
CY28437
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CY28437 Summary of contents
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... SRCT SRCC Divider VDD_SRC Divider SRCT4_SATA SRCC4_SATA VDD_48Mhz Divider DOT96T DOT96C VDD_48 USB48 VDD_PCI PCI VDD_PCI PCIF Watchdog SRESET# Timer Tel:(408) 855-0555 www.DataSheet4U.com CY28437 SRC PCI REF VDD_PCI 2 55 VSS_PCI 3 54 DF2/PCI3 *FS_E/PCI4 4 53 PCI5 5 52 ...
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... MHz clocks/3.3V LVTTL output for Watchdog reset. PU When configured as SRESET# output this output becomes open drain type with a high (>100k ) internal pull-up resistor. I/O, SE 3.3V LVTTL input for Dynamic Frequency/33-MHz clocks output. www.DataSheet4U.com Description when VTT_PWRGD# is asserted LOW. IHFS_C ,V ,V ILFS_C IMFS_C IHFS_C CY28437 specifications. Page ...
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... Tristate Tristate Tristate Tristate Tristate REF/N REF/N REF/N REF/N REF/N Figure 1. CPU and SRC Frequency Select Tables www.DataSheet4U.com CY28437 CPU N SRC PLL SRC M SRC N SRC N allowable Gear divider (not DEFAULT allowable range for Constants changeable range for DAF ...
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... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge .... Stop Byte Read Protocol Bit Description 1 Start 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 20 Repeated start www.DataSheet4U.com CY28437 Page ...
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... CPU[T/C]1 Output Enable 0 = Disable (Tri-state Enabled CPU[T/C]0 Output Enable 0 = Disable (Tri-state Enabled CPU PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off Spread on www.DataSheet4U.com CY28437 Byte Read Protocol Description Slave address – 7 bits Read Acknowledge from slave Data from slave – 8 bits NOT Acknowledge ...
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... RESERVED, Set = 0 PCIF1 Allow control of PCIF1 with assertion of SW PCI_STP Free running Stopped with PCI_STP# PCIF0 Allow control of PCIF0 with assertion of SW PCI_STP Free running Stopped with PCI_STP# RESERVED, Set = 1 RESERVED, Set = 1 RESERVED, Set = 1 www.DataSheet4U.com CY28437 Description Description Description Page ...
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... FS_A Reflects the value of the FS_A pin sampled on power- FS_A was low during VTT_PWRGD# assertion Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 www.DataSheet4U.com CY28437 Description Description Description Page ...
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... WD_Alarm is set to “1” when the watchdog times out reset to “0” when the system clears the WD_TIMER time stamp. Watchdog timer time stamp selection 000: Reserved (test mode) 001 Time_Scale 010 Time_Scale 011 Time_Scale 100 Time_Scale 101 Time_Scale 110 Time_Scale 111 Time_Scale www.DataSheet4U.com CY28437 Description Description Description Page ...
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... SRC Dial-A-Frequency Bit N6 SRC_N5 SRC Dial-A-Frequency Bit N5 SRC_N4 SRC Dial-A-Frequency Bit N4 SRC_N3 SRC Dial-A-Frequency Bit N3 SRC_N2 SRC Dial-A-Frequency Bit N2 SRC_N1 SRC Dial-A-Frequency Bit N1 SRC_N0 SRC Dial-A-Frequency Bit N0 www.DataSheet4U.com CY28437 Description Description Description Description Page ...
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... SRC frequency is selected via the FSE pin 1: SRC frequency is initially set to 167 MHz. RESERVED, Set = 0 SATA PLL Spread Spectrum Enable 0 = Spread off Spread on Programmable SRC frequency enable 0 = Disabled Enabled. Programmable CPU frequency enable 0 = Disabled Enabled Disable (Manual), 1= Enable (Auto) www.DataSheet4U.com CY28437 Description Description Description Page ...
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... AT Parallel The CY28437 requires a parallel resonance crystal. Substi- tuting a series resonance crystal will cause the CY28437 to operate at the wrong frequency and violate the ppm specifi- cation. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading ...
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... By default the smooth switch circuit is assigned to the CPU PLL. Either PLL can still be overclocked when it does not have control of the smooth switch circuit but it is not guaranteed to transition to the new frequency without large frequency glitches. www.DataSheet4U.com CY28437 s. The frequency Page ...
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... RESET pulse on the SRESET# pin. The duration of the SRESET# pulse should be the same as the duration of the SRESET# pulse after a Watchdog timer time out. After the SRESET# pulse is asserted the SW_RESET bit should be automatically cleared by the device. CY28437 Page ...
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... After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Figure example showing the relationship of clocks coming up. Figure 4. Power-down Assertion Timing Waveform Tstable <1.8ms PD Tdrive_PWRDN# <300 S, >200mV Figure 5. Power-down Deassertion Timing Waveform www.DataSheet4U.com CY28437 Page ...
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... VDD_A = 2.0V S0 Power Off Figure 6. Clock Generator Power-up/Run State Diagram Rev 1.0, November 20, 2006 S1 VTT_PWRGD# = Low Delay >0.25mS S3 VDD_A = off Normal Operation VTT_PWRGD# = toggle www.DataSheet4U.com CY28437 S2 Sample Inputs straps Wait for <1.8ms Enable Outputs Page ...
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... SDATA, SCLK SDATA, SCLK Except internal pull-up resistors, 0 < V Except internal pull-down resistors, 0 < – max. load and freq. per Figure 9 PD asserted, Outputs Driven PD asserted, Outputs Tri-state www.DataSheet4U.com CY28437 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD – ...
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... Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX www.DataSheet4U.com CY28437 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10 – 500 ps – ...
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... Measured from 0.525V OH Determined as a fraction of 2*(T – T )/( Math averages Figure 9 Math averages Figure 9 See Figure 9. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V www.DataSheet4U.com CY28437 Min. – OX – = 0.175 to 130 OL – – – 660 –150 250 – –0.3 – ...
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... Measured between 0.8V and 2.0V Measurement at 1.5V Measurement taken from cross point Measurement taken from cross point V @ Measurement taken from cross point V @125 s OX Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V www.DataSheet4U.com CY28437 Min. 0.85 0.85 – – 10.41354 OX 10.16354 OX – OX – OX – – = 0.175 to V ...
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... USB REF Figure 8. Single-ended Load Configuration HIGH DRIVE OPTION Rev 1.0, November 20, 2006 (continued) Condition Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Measurement at 1.5V Figure 7. Single-ended Load Configuration PCI/ USB REF www.DataSheet4U.com CY28437 Min. Max. 0.5 2.0 1.0 4.0 1.0 4.0 – 1000 – 1.8 Measurement Point 5pF ...
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... Package Type www.DataSheet4U.com Product Flow Commercial Commercial Commercial Commercial CY28437 Page ...
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... MAX. 0.20[0.008] 0.051[0.002] 0.152[0.006] 0.170[0.006] SEATING 0.279[0.011] PLANE www.DataSheet4U.com CY28437 DIMENSIONS IN INCHES MIN. MAX. 0.005 .010 0.010 0.024 0.040 0°-8° DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG ...