CY28439 SpectraLinear, CY28439 Datasheet - Page 3

• Manufacturer Part Number: CY28439
• Description: Clock Generator
• Manufacturer: SpectraLinear

Rev 1.0, November 21, 2006
Frequency Select Pins (FS_[A:E])
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C, FS_D, and
FS_E inputs prior to VTT_PWRGD# assertion (as seen by the
clock synthesizer). Upon VTT_PWRGD# being sampled LOW
by the clock chip (indicating processor VTT voltage is stable),
the clock chip samples the FS_A, FS_B, FS_C, FS_D, and
FS_E input values. For all logic levels of FS_A, FS_B, FS_C,
FS_D, and FS_E, VTT_PWRGD# employs a one-shot
functionality in that once a valid LOW on VTT_PWRGD# has
been sampled, all further VTT_PWRGD#, FS_A, FS_B, FS_C,
FS_D, and FS_E transitions will be ignored, except in test
mode. FS_C is a three level input, when sampled at a voltage
greater than 2.1V by VTTPWRGD#, the device will enter test
mode as selected by the voltage level on the FS_B input.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
FS_D
FSEL_3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
X
X
FS_C
FSEL_2
HIGH
HIGH
Input Conditions
1
0
0
0
0
1
1
1
0
0
0
0
1
1
FS_B
FSEL_1
LOW
HIGH
0
0
1
1
0
0
1
0
0
1
1
0
0
1
FS_A
FSEL_0
X
X
1
1
1
0
0
0
0
1
1
1
0
0
0
0
Figure 1. CPU and SRC Frequency Select Tables
133.3333333
166.6666667
266.6666667
333.3333333
266.6666667
400.6451613
100.952381
133.968254
200.952381
Tristate
REF/N
(MHz)
Output Frequency
CPU
100
200
400
167
334
Tristate
REF/N
(MHz)
SRC
100
100
100
100
100
100
100
100
100
100
100
100
100
100
Constants
CPU PLL
Tristate
REF/N
Gear
120
120
120
120
(G)
30
40
60
60
80
30
40
60
60
80
Tristate
CPU M
divider
REF/N
60
60
63
60
60
63
60
63
63
60
63
60
60
62
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
DEFA ULT
Tristate
CPU N
REF/N
200
200
175
200
200
175
200
212
211
167
211
200
167
207
allowable
range for
200 - 250
200 - 250
175 - 262
200 - 250
200 - 250
175 - 262
200 - 250
212 - 262
211 - 262
167 - 250
211 - 262
200 - 250
167 - 250
207 - 258
Tristate
CPU N
REF/N
DAF
Constants
SRC PLL
Gear
30
30
30
30
30
30
30
30
30
30
30
30
30
30
divider (not
changeable
by user)
SRC M
60
60
60
60
60
60
60
60
60
60
60
60
60
60
DEFAULT
SRC N
www.DataSheet4U.com
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 200 - 266
200 167 - 266
200 167 - 266
allowable
range for
SRC N
DAF
CY28439
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