AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 14

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

Overview of Target Microprocessors
2.3.3.1
The bottom three IQ entries are available for dispatch, which involves the following:
2.3.3.2
Each issue queue handles issuing slightly differently and they are described separately as follows.
2.3.3.3
The six-entry general-purpose issue queue (GIQ in Figure 2-5) handles integer instructions, including all
load/store instructions. The GIQ accepts as many as three instructions from the dispatch unit each cycle. All
IU1s, IU2, and LSU instructions (including floating-point and AltiVec loads and stores) are dispatched to
the GIQ. Instructions can be issued out-of-order from the bottom three GIQ entries (GIQ2–GIQ0). An
instruction in GIQ1 destined to one of the IU1s does not have to wait for an instruction stalled in GIQ0 that
is behind a long-latency integer divide instruction in the IU2. The primary check is that a reservation station
must be available.
2.3.3.4
The two-entry floating-point issue queue (FIQ) can accept one dispatched instruction per cycle for the FPU,
and if an FPU reservation station is available, it can also issue one instruction from the bottom FIQ entry.
2.3.3.5
The four-entry vector issue queue (VIQ) accepts as many as two vector instructions from the dispatch unit
each cycle. All AltiVec instructions (other than load, store, and vector touch instructions) are dispatched to
the VIQ. The bottom two entries are allowed to issue as many as two instructions to the four AltiVec
execution unit’s reservation stations, but unlike the GIQ, instructions in the VIQ cannot be issued out of
order. The primary check determines if a reservation station is available.
2.3.3.6
The instruction in the bottom of the reservation station is available for execution. Execution involves the
following:
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Renaming—16 rename registers are available for each of the integer, floating-point, and vector
operations.
Dispatching—Available issue queue entries must be available for each dispatched instruction.
CQ check—An entry must be available in the 16-entry CQ.
Branch check—A branch instruction must have executed before being dispatched. Section 2.3.3.8,
“Branches,” provides more information on branching.
Busy check—The unit must not be busy. For example, some units are not fully pipelined and so
cannot accept a new instruction on every clock.
Dispatch
Issue Queues
General-Purpose Issue Queue
Floating-Point Issue Queue
Vector Issue Queue
Execution
The VIQ can issue to any two vector units, unlike the MPC7400. For
example, the MPC7450 can issue to the VSIU and VCIU simultaneously,
whereas the MPC7400 allows pairing between the VPU and one of the
other three VALU subunits.
MPC7450 RISC Microprocessor Family Software Optimization Guide
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
NOTE
MOTOROLA