AN2203 Freescale Semiconductor / Motorola, AN2203 Datasheet - Page 31

• Manufacturer Part Number: AN2203
• Description: MPC7450 RISC Microprocessor Family Software Optimization Guide
• Manufacturer: Freescale Semiconductor / Motorola

3.4
The following sections describe the conditions for the completion queue such as the re-order sizing, how
the instruction sequence is grouped, and the effects of serialization.
3.4.1
The completion queue size on the MPC7450 is 16 entries. This means that up to 16 instructions can be in
the execution window, not counting branches, which execute from the instruction buffer.
3.4.2
The MPC7450 can retire up to three instructions per cycle. Only three rename registers of a given type can
be retired per cycle. For example, an lwzu, add, subf sequence has four GPR rename targets and all cannot
retire in the same cycle. The lwzu and add retire first and subf retires one cycle later.
3.4.3
The MPC7450 supports refetch, execution, and store serialization. Store serialization is described in
Section 3.7.2, “Store Hit Pipeline.”
Refetch serialized instructions include isync, rfi, sc, mtspr[XER], and any instruction that toggles
XER[SO]. Refetch serialization forces a pipeline flush when the instruction is the oldest in the machine.
These instructions should be avoided in performance-critical code.
Note that XER[SO] is a sticky bit for XER[OV] updates, so avoiding toggling XER[SO] often means
avoiding these instructions (overflow-record, O form).
Execution-serialized instructions wait until the instruction is the oldest in the machine to begin executing.
Tables in Appendix A, “MPC7450 Execution Latencies,” list execution-serialized instructions, which
include mtspr, mfspr, CR logical instructions, and carry consuming instructions (such as adde).
Table 3-14 shows the execution of a carry chain. The addc executes normally and generates a carry. As an
execution-serialized instruction, adde must become the oldest instruction (cycle 4) before it can execute
(cycle 5). A long chain of carry generation/carry consumption can execute at a rate of one instruction every
three cycles.
3.5
The following sections describes how to optimize the use of the execution units.
3.5.1
Each of the three IU1s has one reservation station in which instructions are held until operands are available.
The IU1s allow a potentially large window for out-of-order execution. IU1 instructions can progress until
MOTOROLA
Completion Queue
Numeric Execution Units
Reorder Size
Completion Groupings
Serialization Effects
IU1 Considerations
MPC7450 RISC Microprocessor Family Software Optimization Guide
addc r11,r21,r23
adde r10,r20,r22
Instruction
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 3-14. Serialization Example
Go to: www.freescale.com
D
D
0
1
I
I
—
E
2
—
C
3
—
4
E
5
C
6
Completion Queue
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