CY28439-2 SpectraLinear, CY28439-2 Datasheet - Page 11

• Manufacturer Part Number: CY28439-2
• Description: Clock Generator
• Manufacturer: SpectraLinear

Rev 1.0, November 21, 2006
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs ............................................. Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
CL ................................................... Crystal load capacitance
CLe .........................................Actual loading seen by crystal
using standard value trim capacitors
Ce .....................................................External trim capacitors
Cs ............................................. Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
CLe
Cs1
Total Capacitance (as seen by the crystal)
=
Figure 3. Crystal Loading Example
Ce1
(
Load Capacitance (each side)
Ce1 + Cs1 + Ci1
X1
Ci1
Ce = 2 * CL – (Cs + Ci)
Clock Chip
1
XTAL
Ci2
+
X2
1
Ce2 + Cs2 + Ci2
Ce2
Cs2
1
3 to 6p
33pF
Pin
Trim
2.8pF
Trace
)
Dial-A-Frequency (CPU and SRC)
This feature allows the user to overclock their system by slowly
stepping up the CPU or SRC frequency. When the program-
mable output frequency feature is enabled, the CPU and SRC
frequencies are determined by the following equation
Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M
“N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively. “G” stands for the PLL Gear Constant, which is
determined by the programmed value of FS[E:A]. See
Figure 1 for the Gear Constant for each Frequency selection.
The PCI Express only allows user control of the N register, the
M value is fixed and documented in Figure 1.
In this mode, the user writes the desired N and M value into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the N value if required.
Associated Register Bits
CPU_DAF Enable—This bit enables CPU DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note: the CPU_DAF_N and M register must contain
valid values before CPU_DAF is set. Default = 0, (No DAF).
CPU_DAF_N—There will be nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000) The allowable values for N are detailed in
the frequency select table in Figure 1.
CPU DAF M—There will be 7 bits (for 128 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, the allowable values for M are detailed in the frequency
select table in Figure 1.
SRC_DAF Enable—This bit enables SRC DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the SRC_DAF_N
register. Note: the SRC_DAF_N register must contain valid
values before SRC_DAF is set. Default = 0, (No DAF).
SRC_DAF_N—There are nine bits (for 512 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, (0000) The allowable values for N are detailed in the
frequency select table in Figure 1.
Recovery—The recovery mechanism during CPU DAF when
the system locks up and the Watchdog timer is enabled is
determined by the “Watchdog Recovery Mode” and
“Watchdog Autorecovery Enable” bits. The possible recovery
methods are: (A) Auto, (B) Manual (by Recovery N), (C) HW,
and (D) No recovery, just send reset signal.
There is no recovery mode for SRC Dial-a-Frequency.
Software Frequency Select
This mode allows the user to select the CPU output
frequencies using the Software Frequency select bits in the
SMBUS register.
FSEL—There will be four bits (for 16 combinations) to select
predetermined CPU frequencies from a table. The table selec-
tions are detailed in section Figure 1.
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