CY28441 Cypress Semiconductor, CY28441 Datasheet
CY28441
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CY28441 Summary of contents
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... SRCT0 DOT96T DOT96C SRCC0 USB_48 SRCT1 SRCC1 VDD_SRC SRCT2 SRCC2 SRCT3 SRCC3 SRC4_SATAT SRC4_SATAC VDD_SRC • 3901 North First Street • San Jose CY28441 Alviso Chipset PCI REF DOT96 USB_48 PCI2 2 55 PCI_STP CPU_STP# ...
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... Ground for outputs. GND Ground for PLL. I 3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A, FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for asserting power-down (active HIGH). CY28441 Description ,V specifications. IL_FS IH_FS ,V specifications. ...
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... SRC PCIF/PCI 100 MHz 33 MHz 100 MHz 33 MHz RESERVED Description Bit 1 8 18:11 19 CY28441 Description REF0 DOT96 14.318 MHz 96 MHz 14.318 MHz 96 MHz Block Read Protocol Description Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Acknowledge from slave ...
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... CPU[T/C]2_ITP/SRC[T/C]7 Output Enable 0 = Disable (Hi-Z Enable RESERVED SRC[T/C]5 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]4 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]3 Output Enable 0 = Disable (Hi-Z Enable CY28441 Block Read Protocol Description Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – ...
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... PCIF1 Output Enable 0 = Disabled Enabled Name SRC7 Allow control of SRC[T/C]7 with assertion of PCI_STP PCI_STP Free running Stopped with PCI_STP# RESERVED SRC5 Allow control of SRC[T/C]5 with assertion of PCI_STP PCI_STP Free running Stopped with PCI_STP# CY28441 Description Description Description Description Page ...
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... Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted Name REF/N or Hi-Z Select 0 = Hi- REF/N Clock CY28441 Description Description Description Description Page ...
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... SRC[T/C]4 CLKREQ#A control 1 = SRC[T/C]4 stoppable by CLKREQ#A pin 0 = SRC[T/C]4 not controlled by CLKREQ#A pin SRC[T/C]2 CLKREQ#A control 1 = SRC[T/C]2 stoppable by CLKREQ#A pin 0 = SRC[T/C]2 not controlled by CLKREQ#A pin SRC[T/C]0 CLKREQ#A control 1 = SRC[T/C]0 stoppable by CLKREQ#A pin 0 = SRC[T/C]0 not controlled by CLKREQ#A pin CY28441 Description Description Description Page ...
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... Parallel Crystal Recommendations The CY28441 requires a Parallel Resonance Crystal. Substi- tuting a series resonance crystal will cause the CY28441 to operate at the wrong frequency and violate the ppm specifi- cation. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading ...
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... CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100 and 133 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted HIGH in less than 10 µs after asserting Vtt_PwrGd#. Figure 4. Power-down Assertion Timing Waveform CY28441 Page ...
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... CPUC clock. The final states of the stopped CPU signals are CPUT = HIGH and CPUC = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal (Iref), and the CPUC signal will be Hi-Z. Figure 6. CPU_STP# Assertion Waveform CY28441 Page ...
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... Figure 9. CPU_STP# = Hi-Z, CPU_PD = Hi-Z, DOT_PD = tHi-Z Document #: 38-07679 Rev. ** short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. Tdrive_CPU_STP#,10nS>200mV Figure 7. CPU_STP# Deassertion Waveform CY28441 1.8mS 1.8mS Page ...
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... The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transi- ). (See tions to a high level. (See Figure 11.) SU Tsu Figure 10. PCI_STP# Assertion Waveform Tdrive_SRC Tsu Figure 11. PCI_STP# Deassertion Waveform CY28441 Page ...
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... Sample Sels Delay VTT_PW RGD# State 1 State 2 On Figure 12. VTT_PWRGD# Timing Diagram S1 VTT_PWRGD# = Low Delay >0.25mS S3 VDD_A = off Normal Operation VTT_PWRGD# = toggle CY28441 Device is not affected, VTT_PW RGD# is ignored State Sample Inputs straps Wait for <1.8ms Enable Outputs Page ...
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... SDATA, SCLK SDATA, SCLK Except internal pull-up resistors, 0 < V Except internal pull-down resistors, 0 < – max. load and freq. per Figure 15 PD asserted, Outputs driven PD asserted, Outputs Hi-Z CY28441 Min. Max. Unit –0.5 4.6 –0.5 4.6 –0 0.5 VDC DD –65 150 ° ...
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... T )/( Math averages Figure 15 Math averages Figure 15 See Figure 15. Measure SE Measured at crossing point V OX Measured at crossing point Measured at crossing point V OX Measured at crossing point V OX CY28441 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10 – 500 ps – 300 ppm ...
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... Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured from 0.525V OH Determined as a fraction of 2*(T – T )/( Math averages Figure 15 Math averages Figure 15 See Figure 15. Measure SE CY28441 Min. – OX – OX – 0.175 to 175 – – – 660 –150 250 V – ...
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... Stopclock Hold Time SH Document #: 38-07679 Rev. ** (continued) Condition Measured at crossing point V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V CY28441 Min. Max. Unit 1 20.83125 20.83542 20.48125 21.18542 8.094 10.036 7.694 9.836 1.0 2.0 – ...
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... D iff tia Ω Ω Figure 15. 0.7V Single-ended Load Configuration P robe Load Cap 30pF CY28441 Page ...
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... SEATING 0.279[0.011] PLANE 2 C system, provided that the system conforms to the I CY28441 - Product Flow Commercial, 0 ° ° C Commercial, 0 ° ° C DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG ...
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... Document History Page Document Title: CY28441 Clock Generator for Intel Document Number: 38-07679 REV. ECN NO. Issue Date ** 237792 See ECN Document #: 38-07679 Rev. ** Alviso Chipset Orig. of Change RGL/SDR New Data Sheet CY28441 Description of Change Page ...