CY28441 Cypress Semiconductor, CY28441 Datasheet - Page 10

• Manufacturer Part Number: CY28441
• Description: Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07679 Rev. **
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300 µs of PD deassertion to a voltage greater than 200
mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Figure 5 is an example showing the relationship of
clocks coming up.
CPU_STP#
CPUT
CPUC
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCT 100MHz
USB, 48MHz
PCI, 33MHz
DOT96C
DOT96T
REF
Figure 5. Power-down Deassertion Timing Waveform
PD
Figure 6. CPU_STP# Assertion Waveform
<300µS, >200mV
Tdrive_PWRDN#
Tstable
<1.8nS
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped within two–six CPU clock
periods after being sampled by two rising edges of the internal
CPUC clock. The final states of the stopped CPU signals are
CPUT = HIGH and CPUC = LOW. There is no change to the
output drive current values during the stopped state. The
CPUT is driven HIGH with a current value equal to 6 x (Iref),
and the CPUC signal will be Hi-Z.
CY28441
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