CY28510 SpectraLinear, CY28510 Datasheet
CY28510
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CY28510 Summary of contents
Page 1
... CLKG1_1 Mux VSSQ3 VSSQ2 Mux 2 CLKG1_2 CLKG2_1 CLKG2_0 2 Mux CLKG1_3 VDDQ2 2 Mux CLKG2_0 2 Mux CLKG2_1 2 Mux CLKG3 Tel:(408) 855-0555 Fax:(408) 855-0550 CY28510 VDDQ0 1 48 GFS3 REF 2 47 CLKG0_0 GFS0 3 46 CLKG0_1 VDDX 4 45 VSSQ0 VSSX 5 44 CLKG0_2 XIN 6 43 ...
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... Power supply for outputs. GND Ground for output buffers. PWR 3.3V Power supply for analog PLLs. GND Ground for analog PLLs. PWR 3.3V Power supply for oscillator. GND Ground for oscillator. PWR 3.3V Power supply for core. GND Ground for core. CY28510 Description Page ...
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... Read = 1 29 Acknowledge from slave Byte count from slave – 8 bits 38 Acknowledge Data byte 0 from slave – 8 bits 47 Acknowledge Data byte 1 from slave – 8 bits 56 Acknowledge .... Data bytes from slave/acknowledge .... Data byte N from slave – 8 bits .... Not acknowledge .... Stop CY28510 Page ...
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... Acknowledge from slave 20 Repeat start Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave Data byte from slave – 8 bits 38 Not acknowledge 39 Stop Description CY28510 Page ...
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... KHz KHz KHz KHz Description Description 2 C selection of output [2] SST0 % Spread 0 0 –0.25% Down spread Lexmark profile 0 1 –0.50% Down spread Lexmark profile 1 0 –1.0% Down spread Lexmark profile 1 1 –1.0% Down spread Linear profile CY28510 Page ...
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... CLKG2_1 Frequency select MHz MHz CLKG3 Frequency select MHz MHz DAFEN M and N register mux selection and N values come from the ROM data is loaded from the DAF registers into M and N. CY28510 Description Description Description Description Page ...
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... Crystal Recommendations The CY28510 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28510 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. See Table 6. ...
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... Ce1 + Cs1 + Ci1 should have a separate V The more you can avoid external coupling across VDD planes, the better each sub-net can operate at a different frequency, whether jitter off different frequency. CY28510 Pin Cs2 Trace 2.8pF Trim 33pF ...
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... CLK internal clock edges. Figure 4. CLK_STOP# Assertion Waveforms short or stretched clock pulses will be produced when the clock resumes. The maximum latency from the deassertion to active outputs is no more than 2 CLK clock cycles Figure 5. CLK_STOP# Deassertion Waveforms CY28510 Page ...
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... Measured from the Xin or Xout All outputs disabled running at the default frequency REF buffer with load from Table 7, running at the default frequency 1 CLK buffer with load from Table 7, running at the default frequency Running at the default frequency CY28510 Min. Max. Unit –0.5 5.5 V –0.5 5.5 V –0 0.5 ...
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... Measured at 1.5V with CLKs running different frequencies including within a Sub-group and Spread Spectrum enabled Measured at 1.5V Measured at 1.5V, See Figure 3 Measured from 0.4V to 2.4V, See Figure 3 Measured at 1.5V, See Figure 3 Outputs will be as shown in Figure 3 Max Load (pF CY28510 66 MHz Min. Typ. Max. Unit 200 – 333 MHz 45 – 0.5 – ...
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... Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, November 20, 2006 Measurement Point CLK/REF C LOAD VDDQ 3.3V Figure 6. Output Test Loading Package Type 48-Lead Shrunk Small Outline Package O48 CY28510 Product Flow Commercial Commercial Page ...