AN2269 Freescale Semiconductor / Motorola, AN2269 Datasheet

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AN2269

Manufacturer Part Number
AN2269
Description
Interconnecting MPC8260 and MSC8101 ADS Boards Using DMA Transfers Across a 60x Bus
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
Application Note
AN2269/D
Rev 1, 3/2002
Interconnecting
MPC8260 and
MSC8101 ADS Boards
Using DMA Transfers
Across a 60x Bus
by Scott Smith and
Renaud Le Friec
CONTENTS
1 Device Overview............ 2
1.1 Host MPC8260 Device 2
1.2 MSC8101 Device......... 2
1.3 Device Inter-
2 System Bus–HDI16
2.1 Host Memory
2.2 HDI16 Host Interface.. 3
2.3 Physical
2.4 Host DMA Transfers ... 6
3 HDI16 Device
3.1 Device
3.2 DMA Set-Up................ 9
4 Host Device
4.1 Host Memory
4.2 Host HDI16
4.3 DMA Configuration .. 12
4.4 Host I/O Ports ........... 14
4.5 Start IDMA Loop....... 14
5 Physical ADS Settings . 14
6 Source Code Files,
Host Interface ................ 3
Configuration,
Synchronization, and
Set-Up ............................ 7
Configuration .............. 10
Software Flow, and
Register Settings .......... 15
Operation .................... 3
Controller.................... 3
Interconnections.......... 5
Synchronization........... 8
Controller.................. 11
Registers.................... 12
Within the telecommunications infrastructure, communication between devices is an essential
requirement. For example, banks of DSP resource are often used for applications such as voice
transcoders within basestations, and these devices must have a mechanism for receiving or transmitting
data to or from the outside world. A typical system architecture contains a central controller terminating
protocol layers and distributing the payload to one or more DSP banks (or arrays) for further processing
(see Figure 1). This application note focuses on a subset of the system architecture, describing the
interface between an MPC8260 PowerQUICC II™ device acting as an integrated communications
processor (host) and a single MSC8101 device (called the HDI16 MSC8101) acting as a standard digital
signal processor (DSP) via its 16-bit host parallel interface (HDI16). The host MPC8260 accesses the
HDI16 MSC8101 host interface registers via a memory mapping on its own 60x-compatible bus.
SDRAM
Freescale Semiconductor, Inc.
MSC8101
MSC8101
MSC8101
MSC8101
For More Information On This Product,
RS-232
Figure 1. Controller to Multiple-HDI16 DSP Architecture
Go to: www.freescale.com
Buffer
MPC8260
TDM
UTOPIA
MSC8101
MSC8101
MSC8101
MSC8101
RJ45
PHY
100BaseT
Buffer
MSC8101
MSC8101
MSC8101
MSC8101
Flash
Buffer
60x

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AN2269 Summary of contents

Page 1

... Freescale Semiconductor, Inc. Application Note AN2269/D Rev 1, 3/2002 Interconnecting MPC8260 and MSC8101 ADS Boards Using DMA Transfers Across a 60x Bus by Scott Smith and Within the telecommunications infrastructure, communication between devices is an essential Renaud Le Friec requirement. For example, banks of DSP resource are often used for applications such as voice ...

Page 2

Device Overview 1 Device Overview This section provides a high-level view of the MPC8260 and MSC8101 devices and then describes their inter-operation. 1.1 Host MPC8260 Device The MPC8260 device is a versatile communications processor that integrates a high-performance RISC microprocessor, ...

Page 3

Freescale Semiconductor, Inc. • Multi-channel DMA Controller. Supports time-division multiplexed channels and buffer alignment by hardware. The DMA controller connects to both the system bus and the local bus and can function as a bridge between both ...

Page 4

System Bus–HDI16 Host Interface Internally-Visible Registers HCR HSR HCVR HPCR HOTX HORX NOTE1: Both HOTX and HORX are FIFOs with a capacity of four 64-bit words HCR HSR HCVR ISR ICR CVR 16 16 Registers Visible to Host ...

Page 5

Freescale Semiconductor, Inc. The most important aspect of the HDI16 host interface for our purposes is that it is specified as an asynchronous interface, reducing concerns over clock skew between the HDI16 host interface and the host device buses. Furthermore, ...

Page 6

System Bus–HDI16 Host Interface Table 1. ADS Physical Interconnects (Continued) Host MPC8260 Side System + CPM Edge Connector P16 P4 Pin No. Pin No. Signal Name D31 IDMA2 D32 IDMA1 D10 EXPGPL3 D12 EXPGPL5 B[1–3] C31, C32 0V C1, C3, ...

Page 7

Freescale Semiconductor, Inc. receive and transmit operations, but in Double Request mode, separate requests are possible for transmit and receive ( interrupt inputs consumed on the host processor but the disadvantage of using a single request for both directions. Therefore, ...

Page 8

HDI16 Device Configuration, Synchronization, and Set-Up MPC8260 Host 2 SDRAM IDMA 1 Source 32 Bytes 32 Bytes IDMA DPR Buffers IDMA 2 Destination 32 Bytes Destination 32 Bytes 32 Bytes FIFO empty (HTRQ) write request is ...

Page 9

Freescale Semiconductor, Inc. MPC8260 software. Consequently, the HDI16 MSC8101 side acts as a master during the synchronization process. When the HDI16-side software is ready to process commands sent from the host, it sets signal to the host that it is ...

Page 10

Host Device Configuration external memory or an internal peripheral and internal memory. The HDI16 MSC8101treats the HDI16 interface is an internal peripheral, making it easy to transfer data to and from the HDI16 interface and internal memory. 3.2.3 DMA Interrupts ...

Page 11

Freescale Semiconductor, Inc. To achieve these states, perform the following steps: 1. Configure the host memory controller to enable mapping of the HDI16 registers in memory. 2. Configure the host HDI16 registers, synchronize the host and HDI16 sides, and enable ...

Page 12

Host Device Configuration 4.2 Host HDI16 Registers Once the memory controller is initialized, the HDI16 registers are accessible and configured to meet the needs of this application (see Figure 2 for a list of these registers). Before initializing any of ...

Page 13

Freescale Semiconductor, Inc. The BD associated with IDMA Channel 2 (Host Rx) is configured with the following parameters: • Valid. The BD contains valid data for transfer to be processed. • Wrap. This is the last BD in the BD ...

Page 14

Physical ADS Settings • ERM. Trigger IDMA upon DREQ assertion • S/D. Read from memory/write to memory (the HDI16 interface appears as memory to the host). • SS_MAX. Maximum transfer size is 32 bytes. • STS. Source transfer size is ...

Page 15

... Settings This application was developed using the Metrowerks 1.0. The CodeWarrior IDE provides a set of tools for developing software using a GUI. The Metrowerks project file references an 8101_Initialization.cfg file with which it can configure SDRAM and so on via the debugger. The location of this file can be modified to suit your own implementation of Metrowerks ...

Page 16

Source Code Files, Software Flow, and Register Settings Module Filename VADS8260_MT.reg hdi16.c upminit.c dma.c Mpc8260.h Host MPC8260 hdi16.h hdi16masks.h dma.h dmatest.h for_diab/sbc82xx.lk for_diab/makefile Start Memory-Map HDI16 Core-Side Registers Configure ADS’s Board Control and Status Register (BCSR) Set Host Flag 4 ...

Page 17

Freescale Semiconductor, Inc. Start Store Tx Test Pattern in SDRAM Configure Memory Controller Bank 6 and Option Registers For Memory-Mapping HDI16 Host-Side Registers Load UPMA RAM Array Pattern Send Reset Configuration Word to HDI16 MSC8101 Host Flag 4 Set? No ...

Page 18

Source Code Files, Software Flow, and Register Settings Table 6 and Table 7 present the register settings for the HDI16 MSC8101 device and the host MPC8260 device. Unless indicated otherwise in Table 6, all registers are described in detail in ...

Page 19

Freescale Semiconductor, Inc. Table 6. Register DMA Channel 1 – BD_BSIZE (0) “DMA Programming Model” in the chapter on DMA DMA Channel 1 – DCHCR (0x80014105) “DMA Programming Model” in the chapter on DMA DMA Internal Mask Register (DIMR) (0 ...

Page 20

Source Code Files, Software Flow, and Register Settings Register IDMA 1 Buffer Descriptor – Attributes (0xBA081200) IDMA 1 Buffer Descriptor – Data Length (0x0020) IDMA 1 Buffer Descriptor – Source Data Buffer Pointer (0x4000000) IDMA 1 Buffer Descriptor – Destination ...

Page 21

Freescale Semiconductor, Inc. Table 7. Host MPC8260 Register Settings Register IDMA 2 Parameter RAM – DCM (0x001a) IDMA 2 Parameter RAM – DPR_BUF (0x1800) IDMA 2 Parameter RAM – SS_MAX (0x0020) IDMA 2 Parameter RAM – STS (0x0008) IDMA 2 ...

Page 22

Source Code Files, Software Flow, and Register Settings NOTES: 22 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

Page 23

Freescale Semiconductor, Inc. Source Code Files, Software Flow, and Register Settings NOTES: For More Information On This Product, Go to: www.freescale.com 23 ...

Page 24

... Motorola, Inc. Metrowerks and CodeWarrior are registered trademarks of Metrowerks Corp. in the U.S. and/or other countries. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2002 AN2269/D For More Information On This Product, Go to: www.freescale.com ...

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