AN2269 Freescale Semiconductor / Motorola, AN2269 Datasheet - Page 14

• Manufacturer Part Number: AN2269
• Description: Interconnecting MPC8260 and MSC8101 ADS Boards Using DMA Transfers Across a 60x Bus
• Manufacturer: Freescale Semiconductor / Motorola

Physical ADS Settings
4.4 Host I/O Ports
4.5 Start IDMA Loop
5
14
3
For a detailed description of these registers, consult the Parallel I/O Ports chapter of the MSC8101 Reference Manual.
Physical ADS Settings
• ERM. Trigger IDMA upon DREQ assertion
• S/D. Read from memory/write to memory (the HDI16 interface appears as memory to the host).
• SS_MAX. Maximum transfer size is 32 bytes.
• STS. Source transfer size is 8 bytes.
• DTS. Destination transfer size is 32 bytes.
The registers for the parallel I/O ports are configured to allow the
DMA controller via the DMA Request lines,
enabled on Port C using the following registers:
• Port Pin Assignment Register C (PPARC): bits PC0 and PC1 are set, and all other bits are cleared.
• Port Data Direction Register C (PDIRC): all bits are cleared.
• Port Special Option Register C (PSORC): all bits are cleared.
For cleanliness, the Port C Open-Drain Register (PODRC) and Port Data Register C (PDATC) are also
initialized, with all bits cleared.
Once the memory controller, IDMA BDs, DPR parameters, and IO ports are initialized, the system enters
an infinite while loop that constantly performs the following steps:
1. Issue the IDMA Channel 1 (host 32-byte Tx) start command.
2. Wait for IDMA Channel 1 to complete by checking the IDMA1 BD Complete (BC) bit.
3. Clear the IDMA1 BD Complete bit.
4. Issue the IDMA Channel 2 (host 32-byte Rx) start command.
5. Wait for IDMA Channel 2 to complete by checking the IDMA2 BD Complete (BC) bit.
6. Clear the IDMA2 BD Complete bit.
7. Compare the 32-byte test pattern transmitted by the host to the MSC8101 with the one received, and
8. Increment the first location of the transmit test pattern so that the exact same pattern is not sent every
Table 3 defines the default switch configuration for the HDI16 MSC8101 platform.
record any discrepancies.
time.
SW1 – HOST
SW2 – PPC_CTRL
SW5
Switch
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Table 3. HDI16 MSC8101ADS Switch Settings
On-on-on–on
On-on-on-on-on-on-on-on
32-bit
Settings used
IDMA1
3
:
DREQ
Mandatory to use the HDI16
and
IDMA2
HRRQ
:
DREQ
and
Comments
HTRQ
, respectively, which are
4
signals to reach the