AN2269 Freescale Semiconductor / Motorola, AN2269 Datasheet - Page 2

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AN2269

Manufacturer Part Number
AN2269
Description
Interconnecting MPC8260 and MSC8101 ADS Boards Using DMA Transfers Across a 60x Bus
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
Device Overview
1
1.1 Host MPC8260 Device
1.2 MSC8101 Device
2
Device Overview
This section provides a high-level view of the MPC8260 and MSC8101 devices and then describes their
inter-operation.
The MPC8260 device is a versatile communications processor that integrates a high-performance RISC
microprocessor, a very flexible system integration unit (SIU), and many communications peripheral
controllers for use in a variety of applications, particularly in communications and networking systems.
The core is an embedded variant of the MPC603e microprocessor with 16 KB of instruction cache and 16
KB of data cache and no floating-point unit (FPU). The SIU consists of a flexible memory controller that
interfaces to almost any user-defined memory system and many other peripherals making this device a
complete system on a chip. The communications processor module (CPM) includes all the peripherals
found in the MPC860, with the addition of three high-performance communication channels that support
new emerging protocols (for example, 155-Mbps ATM and Fast Ethernet). The MPC8260 has dedicated
hardware that can handle up to 256 full-duplex, time-division-multiplexed logical channels. Two key
MPC8260 modules that are crucial to the application discussed in this document are as follows:
• Memory controller. Controls a maximum of twelve memory banks shared by a high-performance
• IDMA Emulation. The Communications Processor Module (CPM) can be configured to provide
The 16-bit Motorola MSC8101 processor is the first member of the family of DSPs based on the
StarCore™ SC140 core. On a single device, this very versatile processor integrates the high-performance
SC140 four-ALU (Arithmetic Logic Unit) DSP core with 512 KB of internal memory, a CPM, a 64-bit
60x-compatible bus, an SIU, and a 16-channel DMA controller. With its four-ALU core, the MSC8101
executes up to four multiply-accumulate (MAC) operations in a single clock cycle. The MSC8101 CPM
is a 32-bit RISC-based communications protocol engine that can network to Time-Division Multiplexed
(TDM) highways, Ethernet, and Asynchronous Transfer mode (ATM) backbones. The very large internal
memory, 512 KB, reduces the need for external program and data memories. The MSC8101 offers 1200
DSP MIPS or 3000 RISC MIPS performance using an internal 300 MHz clock with a 1.6 V core and
independent 3.3 V input/output (I/O). MSC8101 power dissipation is estimated at 0.5 W. Two key
MSC8101 modules that are crucial to the application discussed in this document are as follows:
• Host interface (HDI16). A 16-bit wide, full-duplex, double-buffered parallel port that can connect
SDRAM machine, a general-purpose chip-select machine (GPCM), and three user-programmable
machines (UPMs). It supports a glueless interface to synchronous DRAM (SDRAM), SRAM,
EPROM, flash EPROM, burstable RAM, regular DRAM devices, extended data output DRAM
devices, and other peripherals. This flexible memory controller allows the implementation of memory
systems with very specific timing requirements.
general-purpose DMA functionality through the SDMA channel. Four general-purpose independent
DMA (IDMA) channels are supported. In this special emulation mode, the user can specify any
memory-to-memory or peripheral-to/from-memory transfers as if using dedicated DMA hardware.
directly to the data bus of a host processor. The HDI16 supports a variety of buses and gluelessly
connects to a number of industry-standard microcomputers, microprocessors, and DSPs. The HDI16
also supports the 8-bit host data bus, which makes it fully compatible with the DSP56300 HDI08 (as
viewed by the host side, not from the DSP side). The host bus can operate asynchronously to the SC140
core clock, and the HDI16 registers are divided into two banks. The host register bank is accessible to
the external host, and the core register bank is accessible to the SC140 core.
Freescale Semiconductor, Inc.
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